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1. 发明申请

US20080196032A1 HARDWARE DEVICE FOR PROCESSING THE TASKS OF AN ALGORITHM IN PARALLEL 失效
标题翻译：用于处理并行算法的任务的硬件设备
公开(公告)号：US20080196032A1
公开(公告)日：2008-08-14
申请号：US12109001
申请日：2008-04-24
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作

2. 发明授权

US06219416B1 Method and apparatus for processing FISU frames according to the Signalling System 7 protocol 失效
标题翻译：根据信令系统7协议处理FISU帧的方法和装置
公开(公告)号：US06219416B1
公开(公告)日：2001-04-17
申请号：US08807491
申请日：1997-02-27
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： H04M1500
CPC分类号： H04Q3/0025 , H04Q2213/13003 , H04Q2213/13103 , H04Q2213/13174 , H04Q2213/13176 , H04Q2213/13216 , H04Q2213/13305 , H04Q2213/1332 , H04Q2213/13322
摘要： A FISU frame handler which is connected between an adapter and a SS7 low speed network. For each FISU frames transmitted or received in the adapter, an interrupt is generated to a processor located in the adapter. In order to diminish the number of processor interruptions, the FISU frames are externally processed by the FISU frame handler by discarding repeated FISU frames transmitted from the network so as to generate idle state signals to the adapter and by converting idle state signals received from the adapter into repetitive FISU frames to transmit them to the network without interrupting the processor. In order to perform both functions, the FISU frame handler comprises two dedicated hardware units which operate according to specific methods.
摘要翻译：连接在适配器和SS7低速网络之间的FISU帧处理器。对于在适配器中发送或接收的每个FISU帧，将向位于适配器中的处理器生成中断。为了减少处理器中断次数，FISU帧由FISU帧处理器通过丢弃从网络发送的重复的FISU帧来进行外部处理，以便向适配器产生空闲状态信号，并通过转换从适配器接收的空闲状态信号重复的FISU帧将其发送到网络而不中断处理器。为了执行这两个功能，FISU帧处理器包括根据特定方法操作的两个专用硬件单元。

3. 发明授权

US06999994B1 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US06999994B1
公开(公告)日：2006-02-14
申请号：US09606899
申请日：2000-06-29
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F15/16 , G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units.
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作。

4. 发明授权

US06675291B1 Hardware device for parallel processing of any instruction within a set of instructions 有权
标题翻译：用于并行处理一组指令内的任何指令的硬件设备
公开(公告)号：US06675291B1
公开(公告)日：2004-01-06
申请号：US09558792
申请日：2000-04-26
申请人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
IPC分类号： G06F944
CPC分类号： G06F9/38 , G06F9/30145 , G06F9/3822
摘要： Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.
摘要翻译：用于并行处理具有定义操作数字段和其他数据字段的相同格式的一组指令的确定指令的硬件设备，该确定的指令的执行被表示为包括多个处理的算法，其根据决定进行处理。这种设备包括用于激活由指令的操作数字段确定的一个或几个处理（32-38）的处理的装置（22-30），每个与组的特定指令相关联的决策宏块（12-20）的指令，所确定的指令仅选择一个决策marcoblock，以便确定哪些是要激活的进程来执行所确定的指令。

5. 发明授权

US08635620B2 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US08635620B2
公开(公告)日：2014-01-21
申请号：US13365360
申请日：2012-02-03
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9/46 , G06F15/76 , G06F7/38
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.
摘要翻译：一种硬件设备，用于同时处理与包括多个进程的算法相关联的一组固定的预定任务，其中一些进程取决于二进制决策，包括用于处理数据，作出决定和/或处理数据的多个任务单元并作出决定，包括源任务单位和目标任务单位。任务互连逻辑意味着将任务单元互连以将来自源任务单元的动作传送到目的地任务单元。每个任务单元包括处理器，用于响应于接收到的请求动作仅执行与算法相关联的固定的一组预定任务的特定单个任务，以及状态管理器，用于处理源任务单元的动作并构建要发送到目标任务单元的动作。

6. 发明授权

US08607031B2 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US08607031B2
公开(公告)日：2013-12-10
申请号：US13365376
申请日：2012-02-03
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.
摘要翻译：一种硬件设备，用于同时处理与包括多个进程的算法相关联的一组固定的预定任务，其中一些进程取决于二进制决策，包括用于处理数据，作出决定和/或处理数据的多个任务单元并作出决定，包括源任务单位和目标任务单位。任务互连逻辑意味着将任务单元互连以将来自源任务单元的动作传送到目的地任务单元。每个任务单元包括处理器，用于响应于接收到的请求动作仅执行与算法相关联的固定的一组预定任务的特定单个任务，以及状态管理器，用于处理源任务单元的动作并构建要发送到目标任务单元的动作。

7. 发明授权

US06658561B1 Hardware device for executing programmable instructions based upon micro-instructions 有权
标题翻译：用于基于微指令执行可编程指令的硬件设备
公开(公告)号：US06658561B1
公开(公告)日：2003-12-02
申请号：US09553882
申请日：2000-04-20
申请人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
IPC分类号： G06F928
CPC分类号： G06F9/223 , G06F9/30145 , G06F9/30174 , G06F9/30185
摘要： The present invention is directed to a hardware device for parallel processing a determined instruction of a set of programmable instructions having a same format with an operand field defining the execution steps of the instruction corresponding to the execution of micro-instructions, comprising decision blocks (12—20) being each associated with a specific instruction of the set of programmable instructions, only one decision block being selected by the determined instruction in order to define which are the specific micro-instructions to be processed for executing the determined instruction, activation blocks (22-30) respectively associated with the decision blocks for running one or several specific micro-instructions, only the activation block associated with said selected decision block being activated to run the specific micro-instructions, and a micro-instruction selection block (46) connected to each activation block for selecting the specific micro-instructions to be executed.
摘要翻译：本发明涉及一种硬件设备，用于并行处理具有相同格式的一组可编程指令的确定指令，其中操作数字段定义与微指令执行相对应的指令的执行步骤，操作数字段包括判定块（12 -20）各自与所述一组可编程指令的特定指令相关联，所确定的指令仅选择一个判定块，以便确定哪些是要处理的特定微指令用于执行所确定的指令，激活块（分别与用于运行一个或多个特定微指令的判定块相关联，只有与所选择的判定块相关联的激活块被激活以运行特定的微指令，以及微指令选择块（46）连接到每个激活块以选择要执行的特定微指令。

8. 发明授权

US06341346B1 Method for comparison between a pattern sequence and a variable length key 有权
标题翻译：模式序列与可变长度密钥之间进行比较的方法
公开(公告)号：US06341346B1
公开(公告)日：2002-01-22
申请号：US09245182
申请日：1999-02-05
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9305
CPC分类号： G06F9/30018 , G06F9/30021
摘要： A method is disclosed for comparing a pattern sequence with a variable length key. A first bit of this sequence is identified by a pointer, the length and the location of the key are identified by a code word (W, S), the method includes a preliminary step of identifying the sequence and then performing a comparison with the variable length key.
摘要翻译：公开了一种用于将模式序列与可变长度密钥进行比较的方法。该序列的第一位由指针识别，密钥的长度和位置由码字（W，S）标识，该方法包括识别序列，然后与变量进行比较的初步步骤长度键。

9. 发明授权

US07383311B2 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US07383311B2
公开(公告)日：2008-06-03
申请号：US11322378
申请日：2006-01-03
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F15/16 , G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作

10. 发明授权

US06968386B1 System for transferring data files between a user workstation and web server 失效
标题翻译：用于在用户工作站和Web服务器之间传输数据文件的系统
公开(公告)号：US06968386B1
公开(公告)日：2005-11-22
申请号：US09660043
申请日：2000-09-12
申请人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Claude Pin
发明人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Claude Pin
IPC分类号： G06F13/12 , G06F15/167 , G06F15/16 , H04B1/38 , H04L5/16
CPC分类号： G06F13/128
摘要： System for transferring a data file from a web server to a user workstation through a network and reciprocally, the user workstation including a hard disk (205) for storing the data file being transferred over a SCSI bus (208). The user workstation includes a dual-port memory (304) for storing temporarily the data file, a network logic unit (302) interconnected between the network and the input port of the dual-port memory for receiving the data file from the network and transmitting it to the dual-port memory, and a SCSI logic unit (303) interconnected between the output port of the dual-port memory and the SCSI bus for transferring the data file from the dual-port memory to the hard disk over the SCSI bus and reciprocally.
摘要翻译：用于通过网络将数据文件从网络服务器传送到用户工作站的系统，所述用户工作站包括用于存储通过SCSI总线（208）传送的数据文件的硬盘（205）。用户工作站包括用于临时存储数据文件的双端口存储器（304），在网络与双端口存储器的输入端口之间互连的网络逻辑单元（302），用于从网络接收数据文件并发送双端口存储器和在双端口存储器的输出端口和SCSI总线之间互连的SCSI逻辑单元（303），用于通过SCSI总线将数据文件从双端口存储器传送到硬盘并相互地。

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