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1. 发明授权

US06332032B1 Method for generating test files from scanned test vector pattern drawings 失效
标题翻译：从扫描的测试矢量图形图生成测试文件的方法
公开(公告)号：US06332032B1
公开(公告)日：2001-12-18
申请号：US09210529
申请日：1998-12-03
申请人： Gerald T. Michael , Wei Su , Michael A. Dukes
发明人： Gerald T. Michael , Wei Su , Michael A. Dukes
IPC分类号： G06K962
CPC分类号： G06T7/0004 , G01R31/318307 , G06T2207/30141 , G06T2207/30148
摘要： A graphical bitmap image of a scanned test pattern drawing is transformed into a test file in a file format that is readily usable to provide stimuli for computer-aided design (CAD) tools or integrated circuit (IC) testing equipment. A bitmap image of each page of the test pattern drawing is produced as a graphical image of the rows and columns of test pattern data. Non-essential drawing symbols are then removed from the bitmap image, such as the lines used to draw the table. Essential test pattern information is recognized and is converted into a machine readable format by first storing the data in a tabular format having rows and columns which correspond to the rows and columns of the test pattern drawing. The stored test pattern data is then integrated with a machine readable file format which is adaptable to the CAD and IC tool in order to produce the machine readable test file.
摘要翻译：扫描的测试图形图形的图形位图图像被转换成文件格式的测试文件，该文件格式易于用于为计算机辅助设计（CAD）工具或集成电路（IC）测试设备提供刺激。测试图形图的每一页的位图图像被生成为测试图案数据的行和列的图形图像。然后从位图图像中删除非必需的图形符号，例如用于绘制表格的行。基本测试图案信息被识别并通过首先以具有与测试图案图形的行和列对应的行和列的表格格式存储数据而被转换成机器可读格式。然后将存储的测试图案数据与适用于CAD和IC工具的机器可读文件格式集成，以便产生机器可读测试文件。

2. 发明授权

US06314194B1 Method for generating computer aided design programming circuit designs from scanned images of the design 失效
标题翻译：用于从设计的扫描图像生成计算机辅助设计编程电路设计的方法
公开(公告)号：US06314194B1
公开(公告)日：2001-11-06
申请号：US08506943
申请日：1995-07-26
申请人： Gerald T. Michael , Wei Su , Michael A. Dukes
发明人： Gerald T. Michael , Wei Su , Michael A. Dukes
IPC分类号： G06K900
CPC分类号： G06K9/00476 , G06F17/5045
摘要： A VHSIC hardware description language model is generated from a scanned image of an electronic circuit by: a. producing a bitmap image of a schematic using standard scanning devices that takes a paper drawing and produces an image of a drawing in electronic form where the white and black parts of the drawing image are represented by different values, for example, 0 representing white and 1 representing black; locating and identifying the text portions of the schematic which is used later to tag signal and pin names to reassemble hierarchical schematic drawing sets into models where the links between the various schematic drawings are included in the model; locating and identifying the drawing symbols, such as logic gates, transistors, and resistors, as well as the pins that link one schematic drawing to other schematics in a set of drawings, which is used to type each component in the schematic; locating and identifying the signals (or nets) which is a three stage process where the individual signal paths are located and identified, the inversion circles, which are critical to the correct identification of component function, are located and the ports (connections to signals) for each component are located and identified; integrating the information about component type, ports, inversion circles, and fanout (number of input ports driven by an output port) to uniquely identify each component; and combining the component information with the signal information to provide all of the information required to generate the netlist in the desired form (VHDL, Verilog, EDIF, or other).
摘要翻译：通过以下方式从电子电路的扫描图像生成VHSIC硬件描述语言模型：a。使用采用纸张绘制的标准扫描装置产生原理图的位图图像，并以电子形式产生图形的图像，其中绘制图像的白色和黑色部分由不同的值表示，例如0表示白色和1 代表黑色定位和识别原理图的文本部分，其稍后用于标记信号和引脚名称以将分层示意图集合重新组合到模型中，其中各种示意图之间的链接包括在模型中; 定位和识别图形符号，例如逻辑门，晶体管和电阻器，以及将一个示意图链接到一组附图中的其他原理图的引脚，其用于在原理图中键入每个部件; 定位和识别信号（或网络），它们是各个信号路径所在和标识的三个阶段过程，对组件功能的正确识别至关重要的反转圆圈和端口（与信号的连接）为每个组件定位和识别; 集成关于组件类型，端口，反转圆和扇出（由输出端口驱动的输入端口的数量）的信息以唯一地标识每个组件; 以及将组件信息与信号信息组合以提供以所需形式（VHDL，Verilog，EDIF或其他）生成网表所需的所有信息。

3. 发明授权

US5745500A Built-in self testing for the identification of faulty integrated circuit chips in a multichip module 失效
标题翻译：内置自检，用于识别多芯片模块中的故障集成电路芯片
公开(公告)号：US5745500A
公开(公告)日：1998-04-28
申请号：US734819
申请日：1996-10-22
申请人： Thyagaraju Damarla , Moon J. Chung , Wei Su , Gerald T. Michael
发明人： Thyagaraju Damarla , Moon J. Chung , Wei Su , Gerald T. Michael
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318505 , G01R31/2884
摘要： A built-in self test method and circuit identifies a faulty integrated ciit chip in a multichip module. The built-in self test method first applies a test pattern to a multichip module having a plurality of integrated circuit chips and to a reference signal generator, generates a first and second reference signal representing test responses for a fault free multichip module, compresses the outputs from the multichip module into a first and second bit using a first and second linear space compressor, uses exclusive OR logic to combine the first bit with the first reference signal to produce a first fault detection output and to combine the second bit with the second reference signal to produce a second fault detection output, stores the first and second fault detection outputs in a pair of N-bit shift registers; compares the stored outputs to detect a fault condition, and applies a series of recursive logic operations to identify the faulty integrated circuit chip in the multichip module. The built-in self test circuit includes a test pattern generator, a reference signal generator, at least two linear space compressors, at least two N-bit shift registers, and a plurality of logic gates. Identification of the faulty integrated circuit chip in an multichip module using the present invention thereby facilitates the replacement of the specific faulty chip in order to repair the multichip module.
摘要翻译：内置的自检方法和电路识别多芯片模块中的故障集成电路芯片。内置的自检方法首先将测试图案应用于具有多个集成电路芯片的多芯片模块和参考信号发生器，产生表示无故障多芯片模块的测试响应的第一和第二参考信号，压缩输出使用第一和第二线性空间压缩器从多芯片模块进入第一和第二位，使用异或逻辑将第一位与第一参考信号组合以产生第一故障检测输出并将第二位与第二参考信号以产生第二故障检测输出，将第一和第二故障检测输出存储在一对N位移位寄存器中; 比较存储的输出以检测故障状况，并应用一系列递归逻辑运算来识别多芯片模块中的故障集成电路芯片。内置的自检电路包括测试图形发生器，参考信号发生器，至少两个线性空间压缩器，至少两个N位移位寄存器和多个逻辑门。因此，使用本发明的多芯片模块中的故障集成电路芯片的识别便于更换特定故障芯片以便修复多芯片模块。

4. 发明授权

US5946415A Method and apparatus to process drawing images 失效
标题翻译：处理绘图图像的方法和装置
公开(公告)号：US5946415A
公开(公告)日：1999-08-31
申请号：US738502
申请日：1996-10-24
申请人： Wei Su , Gerald T. Michael
发明人： Wei Su , Gerald T. Michael
IPC分类号： G06K9/00 , G06K9/46
CPC分类号： G06K9/00476
摘要： The processing time and memory in converting scanned images to a hardware scription language is significantly reducer by using a "peephole" method to examine only partial images of features of the scanned image that is to be converted. The present method generated minimized feature templates (MFTs) by systematically removing all non-feature image pixels. In particular, the method and apparatus of the present invention establishes pattern estimates from image samples, eliminates unnecessary image pixels using off-line statistical analysis, and extracts feature templates from the larger size image patterns. Pattern recognition is then conducted by processing a few pixels of the unknown image pattern. An application of this technique is to recognize drawing symbols, such as, AND, NAND, OR, NOR, XOR, and XNOR gates, buffers, inverters, registers, and I/O pins from scanned images of electronic drawings.
摘要翻译：通过使用“窥视孔”方法只检查要转换的扫描图像的特征的部分图像，将扫描图像转换为硬件描述语言的处理时间和存储器显着减少。本方法通过系统地去除所有非特征图像像素来生成最小化特征模板（MFT）。特别地，本发明的方法和装置根据图像样本建立模式估计，使用离线统计分析消除不必要的图像像素，并从较大尺寸的图像图案中提取特征模板。然后通过处理未知图像图案的几个像素来进行模式识别。该技术的应用是从电子图纸的扫描图像中识别图形符号，例如AND，NAND，OR，NOR，XOR和XNOR门，缓冲器，反相器，寄存器和I / O引脚。

5. 外观设计

USD996052S1 Gun holster 有权
公开(公告)号：USD996052S1
公开(公告)日：2023-08-22
申请号：US29798430
申请日：2021-07-08
申请人： Wei Su
设计人： Wei Su
摘要： FIG. 1 is a perspective view of a gun holster showing my new design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a left side elevational view thereof;
FIG. 5 is a right side elevational view thereof;
FIG. 6 is a top plan view thereof; and,
FIG. 7 is a bottom plan view thereof.
The broken lines in the drawings depict portions of the gun holster that form no part of the claimed design.

6. 发明授权

US08579437B2 Adaptive sequential wavefront sensor with programmed control 有权
标题翻译：具有编程控制的自适应顺序波前传感器
公开(公告)号：US08579437B2
公开(公告)日：2013-11-12
申请号：US12790301
申请日：2010-05-28
申请人： Wei Su , Yan Zhou
发明人： Wei Su , Yan Zhou
IPC分类号： A61B3/10
CPC分类号： G01J9/00 , A61B3/1015 , A61B3/14 , G01J1/0414 , G01J1/0437
摘要： One embodiment is a machine comprising a sequential wavefront scanner, a variable aperture, a position sensing device and an electronic control and detection system. The electronic control and detection system is configured to control the sequential wavefront scanner to shift the incident wavefront by a set of displacements selected to form a selected scanning pattern to scan the incident wavefront and configured to vary the aperture size to vary detection resolution at different parts of the scanning pattern.
摘要翻译：一个实施例是包括顺序波前扫描仪，可变孔径，位置感测装置和电子控制和检测系统的机器。电子控制和检测系统被配置为控制顺序波前扫描器以将入射波前偏移一组位移，所述位移被选择以形成选择的扫描图案以扫描入射波阵面并且被配置为改变孔径尺寸以改变不同部分处的检测分辨率的扫描图案。

7. 发明授权

US07859194B2 Short arc lamp driver and applications 有权
标题翻译：短弧灯驱动器和应用
公开(公告)号：US07859194B2
公开(公告)日：2010-12-28
申请号：US11590606
申请日：2006-10-30
申请人： Jerry Walker , Arie Ravid , Wei Su , Ronald A. Lesea , Deanna Y. Lesea, legal representative
发明人： Jerry Walker , Arie Ravid , Wei Su , Ronald A. Lesea
IPC分类号： H05B37/02
CPC分类号： H05B41/34 , H05B41/325
摘要： A short arc lamp driving circuit includes a trigger boosting circuit, a flash current control circuit, and a closed loop exposure control and calibration circuits that, when combined, can produce short pulses of light with short time separation, quasi-continuous illumination light, and meanwhile, an extremely large dynamic range of delivered and/or calibrated light power or energy.
摘要翻译：短弧灯驱动电路包括触发升压电路，闪光电流控制电路和闭环曝光控制和校准电路，当组合时，可以产生具有短时间间隔的短脉冲光，准连续照明光和同时，交付和/或校准的光功率或能量的动态范围非常大。

8. 发明申请

US20080123052A1 Delivering a short Arc lamp light for eye imaging 失效
标题翻译：为眼睛成像提供短弧灯
公开(公告)号：US20080123052A1
公开(公告)日：2008-05-29
申请号：US11606597
申请日：2006-11-29
申请人： Wei Su , Yan Zhou , Yeou-Yen Cheng , Qing Chun Zhao
发明人： Wei Su , Yan Zhou , Yeou-Yen Cheng , Qing Chun Zhao
IPC分类号： A61B3/10
CPC分类号： A61B3/0008 , A61B3/12
摘要： A light delivery technique includes optical configurations as well as the associated methods that generate a ring beam from a linear light source. In one embodiment, a remote light source module delivers illumination light to a fundus camera and/or slit lamp. In another embodiment, an arrangement combines the use of a light pipe homogenizer and a ring beam transformer for efficiently collecting light from a substantially axially linear light source, homogenizing the collected light that lacks low angle flux relative to the optical axis, and transforming the light into a ring beam with a substantially improved low angle flux distribution. In still another embodiment, light emitted from a substantially axially linear light source is directly collected by a curved surface mirror and spatially filtered into a ring beam. The ring illumination beam can be co-axially projected on a sample such as the pupil of a human eye and at the same time the light beam also has a large enough relatively uniform angular flux distribution so that a wide area on the retina of the eye can be uniformly illuminated.
摘要翻译：光输送技术包括光学配置以及从线性光源产生环形光束的相关方法。在一个实施例中，远程光源模块将照明光传送到眼底照相机和/或裂隙灯。在另一个实施例中，一种布置结合了光管均质器和环形光束变换器的使用，用于有效地收集来自基本轴向线性光源的光，使收集到的光相互均匀化，所述光相对于光轴缺少低角度通量，以及将光转换成为具有基本上改进的低角度通量分布的环形梁。在另一个实施例中，从基本轴向线性光源发射的光直接由弯曲表面镜收集，并在空间上过滤成环形光束。环形照明光束可以同轴地投射在诸如人眼的瞳孔的样品上，并且同时光束也具有足够大的相对均匀的角度通量分布，使得眼睛的视网膜上的广泛区域可以均匀照明。

9. 发明授权

US07184937B1 Signal repetition-rate and frequency-drift estimator using proportional-delayed zero-crossing techniques 失效
标题翻译：使用比例延迟过零技术的信号重复率和频率漂移估计器
公开(公告)号：US07184937B1
公开(公告)日：2007-02-27
申请号：US11183219
申请日：2005-07-14
申请人： Wei Su , John A. Kosinski
发明人： Wei Su , John A. Kosinski
IPC分类号： G06F15/00
CPC分类号： H03K5/1536 , G01R23/02 , H04L27/0014 , H04L2027/0046
摘要： Proportional-delayed zero-crossing frequency-drift estimator devices are provided. Given N-number of time samples, the current zero-crossing time estimation technique uses only two zero-crossing time samples for repetition-rate estimation. The term “zero-crossing point” refers to the point where a sinusoidal waveform varies from a positive to a negative value and crosses the zero value in the process. The proportional-delayed zero-crossing frequency-drift estimator devices employ four zero-crossing time samples by utilizing both proportional zero-crossing points for current information and delayed zero-crossing points for past information so that the noises in the time samples will be smoothed out making a less noisy estimation. The proportional-delayed zero-crossing frequency-drift estimators are composed of a hysteretic nonlinear converter, a zero-crossing time-difference counter, a group of shift registers and adders, a repetition-rate algorithm, a reciprocal operator and a means for differentiation operation. A number of different embodiments are provided, but all embodiments include a hysteretic nonlinear converter which enhances the zero-crossing features and blocks the signal random noise so that the zero-crossing point is measured more accurately.
摘要翻译：提供比例延迟的过零频率漂移估计器件。给定N个时间样本，当前的过零时间估计技术仅使用两个过零时间样本进行重复率估计。术语“过零点”是指正弦波形从正值到负值变化的点，并且在过程中跨过零值。比例延迟过零频率漂移估计器件通过利用电流信息的两个比例过零点和过去信息的延迟过零点来采用四个过零时间样本，使得时间样本中的噪声将被平滑做出较不嘈杂的估计。比例延迟过零频率漂移估计器由滞后非线性转换器，零交叉时差计数器，一组移位寄存器和加法器组成，重复率算法，互易算子和分化手段操作。提供了许多不同的实施例，但是所有实施例都包括滞后非线性转换器，其增强过零特征并阻止信号随机噪声，从而更准确地测量过零点。

10. 发明授权

US07133791B1 Two-mean level-crossing time interval estimation method 失效
标题翻译：双平均电平交叉时间间隔估计方法
公开(公告)号：US07133791B1
公开(公告)日：2006-11-07
申请号：US11102447
申请日：2005-03-31
申请人： Wei Su
发明人： Wei Su
IPC分类号： G06F15/00 , G01D18/00 , H03F1/26
CPC分类号： G01R23/10
摘要： N-sample level-crossing estimator methods and devices are provided that extract more information from given time samples than the current two-sample approach and that are more resistant to interference from noises. The two-mean level-crossing time-interval estimation method extracts more information from given time samples than existing methods, advantageously estimates a level-crossing time interval with a limited number of time samples and is quieter than current noisy estimation techniques. The two-mean level crossing time-interval estimation method for N-sample estimation uses all N time samples by calculating the mean value of the first N/2 time samples and subtracting it by the second N/2 time sample to average out the noises in time samples. The two-mean level crossing time-interval estimation method can be implemented by using a Finite Impulse Response filter to take level-crossing time samples as inputs, take the differential level-crossing time samples as inputs, or take the N/2-step differential level-crossing time-interval as an input. An addition only one-step differential level-crossing time-interval estimator device and a one-step differential level-crossing time-interval estimator device are also provided.
摘要翻译：提供了N个采样级别交叉估计器方法和装置，其从给定的时间样本中提取比目前的两个样本方法更多的信息，并且更能抵抗来自噪声的干扰。双平均电平交叉时间间隔估计方法从现有方法中提取给定时间样本的更多信息，有利地估计具有有限数量的时间样本的电平交叉时间间隔，并且比当前噪声估计技术更安静。用于N样本估计的两平均电平交叉时间间隔估计方法通过计算第一N / 2个时间采样的平均值并且通过第二N / 2个时间采样来减去噪声来使用所有N个时间采样在时间样本。可以通过使用有限脉冲响应滤波器来实现两平均电平交叉时间间隔估计方法，以将电平交叉时间采样作为输入，将差分电平交叉时间采样作为输入，或采取N / 2步差分电平交叉时间间隔作为输入。还提供了仅一步差分电平交叉时间间隔估计器装置和一步差分电平交叉时间间隔估计器装置。

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