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1. 发明申请

US20080052491A1 Manifold Array Processor 失效
标题翻译：歧管阵列处理器
公开(公告)号：US20080052491A1
公开(公告)日：2008-02-28
申请号：US11830357
申请日：2007-07-30
申请人： Gerald Pechanek , Charles Kurak
发明人： Gerald Pechanek , Charles Kurak
IPC分类号： G06F15/80
CPC分类号： G06F15/17381 , G06F9/30076 , G06F15/17337 , G06F15/8023
摘要： An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torus may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port (35) and a single receive port (37). Thus, the individual PEs are decoupled from the array topology.
摘要翻译：阵列处理器包括以簇（例如，44,46,48）排列的处理元件（00,01,02,03,10,11,12,13,20,21,22,23,30,31,32,33），50）以形成矩形阵列（40）。群集间通信路径（88）是互斥的。由于数据路径的相互独占性，每个集群的处理元件之间的通信可以组合在单个集群间路径中，从而消除路径所需的一半接线。最长通信路径的长度不直接取决于阵列的整体尺寸，如在常规环形阵列中。相反，最长的通信路径受群间间隔的限制。 NxN环面的转置元素可以组合在一起并通过集群内通信路径相互通信。这种方法消除了转置操作延迟。每个PE可以具有单个发送端口（35）和单个接收端口（37）。因此，各个PE与阵列拓扑分离。

2. 发明申请

US20050125644A1 Specifying different type generalized event and action pair in a processor 失效
标题翻译：在处理器中指定不同类型的广义事件和动作对
公开(公告)号：US20050125644A1
公开(公告)日：2005-06-09
申请号：US10786604
申请日：2004-02-25
申请人： Edwin Barry , Patrick Marchand , Gerald Pechanek , Charles Kurak
发明人： Edwin Barry , Patrick Marchand , Gerald Pechanek , Charles Kurak
IPC分类号： G06F9/00 , G06F9/30 , G06F9/32 , G06F15/00
CPC分类号： G06F9/30054 , G06F9/30101 , G06F9/30112 , G06F9/325
摘要： A processor with a generalized eventpoint architecture, which is scalable for use in a very long instruction word (VLIW) array processor, such as the manifold array (ManArray) processor is described. In one aspect, generalized processor event (p-event) detection facilities are provided by use of compares to check if an instruction address, a data memory address, an instruction, a data value, arithmetic-condition flags, or other processor change of state eventpoint has occurred. In another aspect, generalized processor action (p-action) facilities are provided to cause a change in the program flow by loading the program counter with a new instruction address, generate an interrupt, signal a semaphore, log or count the p-event, time stamp the event, initiate a background operation, or to cause other p-actions to occur. The generalized facilities are defined in the eventpoint architecture as consisting of a control register and three eventpoint parameters, namely at least one register to compare against, a register containing a second compare register, a vector address, or parameter to be passed, and a count or mask register. Based upon this generalized eventpoint architecture, new capabilities are enabled. For example, auto-looping with capabilities to branch out of a nested auto-loop upon detection of a specified condition, background DMA facilities, the ability to link a chain of p-events together for debug purposes, and others are all important capabilities which are readily obtained.
摘要翻译：描述了具有广泛事件点架构的处理器，其可扩展以用于非常长的指令字（VLIW）阵列处理器，例如歧管阵列（ManArray）处理器。在一个方面，通过使用比较来提供广义处理器事件（p事件）检测设施，以检查指令地址，数据存储器地址，指令，数据值，算术条件标志或其他处理器状态变化事件点已发生。在另一方面，提供通用处理器动作（p-action）功能以通过用新的指令地址加载程序计数器来产生程序流程的改变，生成中断，信号信号，记录或计数p事件，事件时间戳，启动后台操作，或导致其他动作发生。广义设施在事件点架构中被定义为由控制寄存器和三个事件点参数组成，即至少要有一个要比较的寄存器，一个包含第二个比较寄存器的寄存器，一个向量地址或要传递的参数，以及一个计数或屏蔽寄存器。基于这种广义的事件点架构，启用了新的功能。例如，在检测到指定的条件时，自动循环具有分支出嵌套自动循环的功能，后台DMA设施，将p个事件链链接在一起用于调试目的的能力等等都是重要的功能容易获得。

3. 发明申请

US20070150698A1 Manifold Array Processor 失效
标题翻译：歧管阵列处理器
公开(公告)号：US20070150698A1
公开(公告)日：2007-06-28
申请号：US11682948
申请日：2007-03-07
申请人： Gerald Pechanek , Charles Kurak
发明人： Gerald Pechanek , Charles Kurak
IPC分类号： G06F15/00
CPC分类号： G06F15/17381 , G06F9/30076 , G06F15/17337 , G06F15/8023
摘要： An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather, the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torts may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port (35) and a single receive port (37). Thus, the individual PEs are decoupled from the array topology.
摘要翻译：阵列处理器包括以簇（例如，44,46,48,50）排列的处理元件（00,01,02,03,10,11,12,13,20,21,23,30,31,32,33））以形成矩形阵列（40）。群集间通信路径（88）是互斥的。由于数据路径的相互独占性，每个集群的处理元件之间的通信可以组合在单个集群间路径中，从而消除路径所需的一半接线。最长通信路径的长度不直接取决于阵列的整体尺寸，如在常规环形阵列中。相反，最长的通信路径受群间间隔的限制。 NxN侵权的转置元素可以组合在一起并通过集群内通信路径相互通信。这种方法消除了转置操作延迟。每个PE可以具有单个发送端口（35）和单个接收端口（37）。因此，各个PE与阵列拓扑分离。

4. 发明申请

US20070154104A1 Methods and Apparatus for Video Decoding 失效
标题翻译：视频解码方法与装置
公开(公告)号：US20070154104A1
公开(公告)日：2007-07-05
申请号：US11671236
申请日：2007-02-05
申请人： Doina Petrescu , Trampas Stern , Marco Jacobs , Dan Searles , Charles Kurak
发明人： Doina Petrescu , Trampas Stern , Marco Jacobs , Dan Searles , Charles Kurak
IPC分类号： G06K9/36
CPC分类号： H04N19/42 , H04N19/436 , H04N19/44 , H04N19/61
摘要： Techniques for performing the processing of blocks of video in multiple stages. Each stage is executed for blocks of data in the frame that need to go through that stage, based on the coding type, before moving to the next stage. This order of execution allows blocks of data to be processed in a nonsequential order, unless the blocks need to go through the same processing stages. Multiple processing elements (PEs) operating in SIMD mode executing the same task and operating on different blocks of data may be utilized, avoiding idle times for the PEs. In another aspect, inverse scan and dequantization operations for blocks of data are merged in a single procedure operating on multiple PEs operating in SIMD mode. This procedure makes efficient use of the multiple PEs and speeds up processing by combining two operations, inverse scan (reordering) and dequantization, which load the execution units differently. The reordering loads mainly the load and store units of the PEs, while the dequantization loads mainly other units. By combining the inverse scan and dequantization in an efficient VLIW packing performance, processing gain is achieved.
摘要翻译：用于在多个阶段中执行视频块处理的技术。在移动到下一阶段之前，根据编码类型，在需要经过该阶段的帧中的数据块执行每个阶段。这种执行顺序允许以非顺序的顺序处理数据块，除非块需要经历相同的处理阶段。可以利用以SIMD模式运行的执行相同任务并在不同的数据块上操作的多个处理元件（PE），避免了PE的空闲时间。在另一方面，用于数据块的逆扫描和去量化操作在以在SIMD模式下操作的多个PE上操作的单个过程中合并。该过程有效地利用多个PE，并通过组合两个操作，反向扫描（重新排序）和去量化来加快处理，从而不同地加载执行单元。重新排序负载主要是PE的负载和存储单元，而反量化主要负载其他单元。通过在有效的VLIW包装性能中组合逆扫描和去量化，实现了处理增益。

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