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1. 发明申请

US20080120494A1 Methods and Apparatus for a Bit Rake Instruction 有权
标题翻译：位耙指令的方法和装置
公开(公告)号：US20080120494A1
公开(公告)日：2008-05-22
申请号：US12021538
申请日：2008-01-29
申请人： Patrick Marchand , Gerald Pechanek , Edward Wolff
发明人： Patrick Marchand , Gerald Pechanek , Edward Wolff
IPC分类号： G06F9/30 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30036 , G06F9/30079 , G06F9/30083 , G06F9/3012 , G06F9/30141 , G06F9/3853 , G06F9/3885 , Y02D10/128 , Y02D10/171
摘要： Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.
摘要翻译：在可扩展数组间接VLIW处理器中提供低功耗架构特性和技术。这些特征和技术包括可重配置寄存器文件的功率控制，多周期操作的条件功率控制和间接VLIW利用，以及使用ManArray寄存器文件索引机制的基于VLIW的向量处理的功率控制。这些技术适用于所有处理元件（PE）和阵列控制器序列处理器（SP），以提供显着的功率节省。

2. 发明申请

US20080052491A1 Manifold Array Processor 失效
标题翻译：歧管阵列处理器
公开(公告)号：US20080052491A1
公开(公告)日：2008-02-28
申请号：US11830357
申请日：2007-07-30
申请人： Gerald Pechanek , Charles Kurak
发明人： Gerald Pechanek , Charles Kurak
IPC分类号： G06F15/80
CPC分类号： G06F15/17381 , G06F9/30076 , G06F15/17337 , G06F15/8023
摘要： An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torus may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port (35) and a single receive port (37). Thus, the individual PEs are decoupled from the array topology.
摘要翻译：阵列处理器包括以簇（例如，44,46,48）排列的处理元件（00,01,02,03,10,11,12,13,20,21,22,23,30,31,32,33），50）以形成矩形阵列（40）。群集间通信路径（88）是互斥的。由于数据路径的相互独占性，每个集群的处理元件之间的通信可以组合在单个集群间路径中，从而消除路径所需的一半接线。最长通信路径的长度不直接取决于阵列的整体尺寸，如在常规环形阵列中。相反，最长的通信路径受群间间隔的限制。 NxN环面的转置元素可以组合在一起并通过集群内通信路径相互通信。这种方法消除了转置操作延迟。每个PE可以具有单个发送端口（35）和单个接收端口（37）。因此，各个PE与阵列拓扑分离。

3. 发明申请

US20060218376A1 METHODS AND APPARATUS FOR EFFICIENTLY SHARING MEMORY AND PROCESSING IN A MULTI-PROCESSOR 有权
标题翻译：在多处理器中有效地共享存储器和处理的方法和装置
公开(公告)号：US20060218376A1
公开(公告)日：2006-09-28
申请号：US11277507
申请日：2006-03-26
申请人： Gerald Pechanek
发明人： Gerald Pechanek
IPC分类号： G06F15/00
CPC分类号： G06F15/8023 , G06F9/3001 , G06F9/30043 , G06F9/30145 , G06F9/30163 , G06F9/30167 , G06F9/3887 , G06F15/17393
摘要： A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify any source operand addresses or target operand addresses. The source operands and target operands for arithmetic/logic execution units are provided by independent load instruction operations and independent store instruction operations.
摘要翻译：描述了一种用于使用存储和加载指令在处理器之间进行通信的共享存储器网络。还描述了可以与共享存储器网络一起使用的新的处理器架构，其使用不指定任何源操作数地址或目标操作数地址的算术/逻辑指令。算术/逻辑执行单元的源操作数和目标操作数由独立的加载指令操作和独立存储指令操作提供。

4. 发明申请

US20050027973A1 Methods and apparatus for scalable array processor interrupt detection and response 有权
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US20050027973A1
公开(公告)日：2005-02-03
申请号：US10931751
申请日：2004-09-01
申请人： Edwin Barry , Patrick Marchand , Gerald Pechanek , Larry Larsen
发明人： Edwin Barry , Patrick Marchand , Gerald Pechanek , Larry Larsen
IPC分类号： G06F9/00 , G06F9/38 , G06F9/48 , G06F13/24 , G06F13/26
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。

5. 发明申请

US20050055539A1 Methods and apparatus for general deferred execution processors 有权
标题翻译：一般延期执行处理器的方法和装置
公开(公告)号：US20050055539A1
公开(公告)日：2005-03-10
申请号：US10773673
申请日：2004-02-06
申请人： Gerald Pechanek , Stamatis Vassiliadis
发明人： Gerald Pechanek , Stamatis Vassiliadis
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/38 , G06F9/3802
摘要： Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.
摘要翻译：描述了用于将存储在主程序存储器中的指令的取出与指令的最早执行解耦的技术。解决了支持这种执行的间接执行方法和程序指令。此外，描述了一种改进的间接延迟执行处理器（DXP）VLIW架构，其支持不需要本地加载和存储单元的可扩展阵列的存储器中心处理器元件。

6. 发明申请

US20070150698A1 Manifold Array Processor 失效
标题翻译：歧管阵列处理器
公开(公告)号：US20070150698A1
公开(公告)日：2007-06-28
申请号：US11682948
申请日：2007-03-07
申请人： Gerald Pechanek , Charles Kurak
发明人： Gerald Pechanek , Charles Kurak
IPC分类号： G06F15/00
CPC分类号： G06F15/17381 , G06F9/30076 , G06F15/17337 , G06F15/8023
摘要： An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather, the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torts may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port (35) and a single receive port (37). Thus, the individual PEs are decoupled from the array topology.
摘要翻译：阵列处理器包括以簇（例如，44,46,48,50）排列的处理元件（00,01,02,03,10,11,12,13,20,21,23,30,31,32,33））以形成矩形阵列（40）。群集间通信路径（88）是互斥的。由于数据路径的相互独占性，每个集群的处理元件之间的通信可以组合在单个集群间路径中，从而消除路径所需的一半接线。最长通信路径的长度不直接取决于阵列的整体尺寸，如在常规环形阵列中。相反，最长的通信路径受群间间隔的限制。 NxN侵权的转置元素可以组合在一起并通过集群内通信路径相互通信。这种方法消除了转置操作延迟。每个PE可以具有单个发送端口（35）和单个接收端口（37）。因此，各个PE与阵列拓扑分离。

7. 发明申请

US20070180440A1 Methods and Apparatus for Meta-Architecture Defined Programmable Instruction Fetch Functions Supporting Assembled Variable Length Instruction Processors 有权
标题翻译：元结构定义的可编程指令获取功能的方法和设备支持组装的可变长度指令处理器
公开(公告)号：US20070180440A1
公开(公告)日：2007-08-02
申请号：US11677640
申请日：2007-02-22
申请人： Gerald Pechanek
发明人： Gerald Pechanek
IPC分类号： G06F9/45
CPC分类号： G06F9/3853 , G06F9/325 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3842 , G06F9/3885
摘要： A computing architecture and software techniques are described which modifies the basic sequential instruction fetching mechanism of a processor by separating a program's control flow from its functional execution flow. A compiled sequential HLL program's static control structures are analyzed and a separate program based on its own unique instructions is created that primarily generates addresses for the selection of functional execution instructions. The original program is now represented by an instruction fetch program and a set of function/logic execution instructions. This basic split allows multiple instruction addresses to be generated in parallel to access multiple instruction memories. These multiple instruction memories contain only the function/logic instructions of the program and no control structure operations such as branches or calls. All the original program's control instructions are split from the original program and used to create the instruction addressing program. This approach allows a variable number of instructions to be issued in parallel whenever the program can allow for it. The instructions of this approach are referred to herein as assembled variable length instructions or AVLIs. Alternative techniques are provided that deal with conditional and unconditional branches. In addition, all or a majority of duplicate function/logic instructions can be removed relying on a single copy or a small number of copies to be stored and referenced as needed by the control program based on architecture features so that overall instruction storage can be reduced.
摘要翻译：描述了通过将程序的控制流与其功能执行流分离来修改处理器的基本顺序指令获取机制的计算架构和软件技术。分析编译的顺序HLL程序的静态控制结构，并创建基于其自己的唯一指令的独立程序，主要生成用于选择功能执行指令的地址。原始程序现在由指令获取程序和一组功能/逻辑执行指令表示。该基本分割允许并行产生多个指令地址以访问多个指令存储器。这些多指令存储器仅包含程序的功能/逻辑指令，并且不包括诸如分支或调用的控制结构操作。所有原始程序的控制指令都是从原始程序中分离出来的，用于创建指令寻址程序。这种方法允许在程序可以允许的情况下并行发出可变数量的指令。这种方法的说明在这里被称为组装的可变长度指令或AVLI。提供了处理有条件和无条件分支的替代技术。另外，根据架构特征，控制程序根据需要存储和引用单个副本或少量副本，可以删除所有或大部分的重复功能/逻辑指令，从而可以减少总体指令存储。

8. 发明申请

US20060224656A1 Methods and apparatus for efficient complex long multiplication and covariance matrix implementation 失效
公开(公告)号：US20060224656A1
公开(公告)日：2006-10-05
申请号：US11438418
申请日：2006-05-22
申请人： Gerald Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
发明人： Gerald Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
IPC分类号： G06F7/52
CPC分类号： G06F7/4812 , G06F9/30014 , G06F9/325 , G06F9/3885 , G06F17/15 , G06F17/16 , G06F2207/3896
摘要： Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

9. 发明申请

US20060150170A1 Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture 有权
标题翻译：用于自动生成缩写指令集和可配置处理器架构的方法和装置
公开(公告)号：US20060150170A1
公开(公告)日：2006-07-06
申请号：US11340072
申请日：2006-01-26
申请人： Sergei Larin , Gerald Pechanek , Thomas Conte
发明人： Sergei Larin , Gerald Pechanek , Thomas Conte
IPC分类号： G06F9/45
CPC分类号： G06F9/30178 , G06F8/447 , G06F9/30156 , G06F9/30167
摘要： A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processor using today's technology without posing significant strain on timing requirements.
摘要翻译：描述了嵌入式处理器中的指令获取机制和指令集架构的架构和设计的系统方法。这种系统的方法允许放松通常由固定大小的指令集架构（ISA）对嵌入式系统的设计和开发施加的某些限制。该方法还保证可用指令存储器的高效使用，该指令存储器仅由应用程序或其熵的实际信息内容限定。这种效率提高的结果是原始应用的指令段的存储要求或压缩的普遍降低。该系统的另一个特点是ISA与核心架构的完全解耦。这种去耦允许对任何大小的ISA使用可变长度编码，而不会影响物理指令存储器组织或布局和分支机制，以及将执行核心调整到应用程序。本文描述的硬件实施例允许在现有技术的实际嵌入式处理器中应用上述高熵编码技术，而不会对定时要求造成显着的压力。

10. 发明申请

US20050223253A1 Methods and apparatus for power control in a scalable array of processor elements 有权
标题翻译：处理器元件可扩展阵列中功率控制的方法和装置
公开(公告)号：US20050223253A1
公开(公告)日：2005-10-06
申请号：US11128742
申请日：2005-05-13
申请人： Patrick Marchand , Gerald Pechanek , Edward Wolff
发明人： Patrick Marchand , Gerald Pechanek , Edward Wolff
IPC分类号： G06F1/08 , G06F1/32 , G06F9/30 , G06F9/38 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/30036 , G06F9/30101 , G06F9/3853 , G06F9/3885 , G06F9/3891 , Y02D10/128
摘要： Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.
摘要翻译：在可扩展数组间接VLIW处理器中提供低功耗架构特性和技术。这些特征和技术包括可重配置寄存器文件的功率控制，多周期操作的条件功率控制和间接VLIW利用，以及使用ManArray寄存器文件索引机制的基于VLIW的向量处理的功率控制。这些技术适用于所有处理元件（PE）和阵列控制器序列处理器（SP），以提供显着的功率节省。

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