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1. 发明授权

US06693031B2 Formation of a metallic interlocking structure 失效
标题翻译：形成金属互锁结构
公开(公告)号：US06693031B2
公开(公告)日：2004-02-17
申请号：US10039710
申请日：2002-01-04
申请人： Gerald G. Advocate, Jr. , Francis J. Downes, Jr. , Luis J. Matienzo , Ronald A. Kaschak , John S. Kresge , Daniel C. Van Hart
发明人： Gerald G. Advocate, Jr. , Francis J. Downes, Jr. , Luis J. Matienzo , Ronald A. Kaschak , John S. Kresge , Daniel C. Van Hart
IPC分类号： H01L2144
CPC分类号： H01L23/5226 , H01L23/49827 , H01L2924/0002 , H05K3/0035 , H05K3/027 , H05K3/06 , H05K3/383 , H05K3/421 , H05K3/4644 , H05K2201/0248 , H05K2201/09509 , H05K2201/09563 , H05K2203/0307 , H05K2203/0353 , H01L2924/00
摘要： An electronic structure including a metallic interlocking structure for bonding a conductive plated layer to metal surface, and a method of forming the electronic structure. The method provides a substrate having a metallic sheet within a dielectric layer. The metallic sheet includes a metal such as copper. An opening in the substrate, such as a blind via, is formed by laser drilling through the dielectric layer and partially through the metallic sheet. If the opening is a blind via, then the laser drilling is within an outer ring of the blind via cross section using a laser beam having a target diameter between about 20% and about 150% of a radius of the blind via cross section. A surface at the bottom of the opening, called a “blind surface,” includes a metallic protrusion formed by the laser drilling, such that the metallic protrusion is integral with a portion of the blind surface. The metallic protrusion includes the metal of the metallic sheet and at least one constituent element from the dielectric layer. The metallic protrusion is then etched to form a metallic interlocking structure that is integral with the portion of the blind surface. The metallic interlocking structure includes discrete metallic fibers, with each metallic fiber having a curved (or curled) geometry. Each metallic fiber has its own unique composition that includes the metal, at least one constituent element of the dielectric layer, or both.
摘要翻译：一种电子结构，包括用于将导电镀层接合到金属表面的金属互锁结构，以及形成电子结构的方法。该方法提供了在电介质层内具有金属片的衬底。金属片包括铜等金属。通过激光钻孔穿过电介质层并且部分地穿过金属片，形成诸如盲孔之类的衬底中的开口。如果开口是盲孔，则激光钻孔是通过横截面的盲孔通过横截面的半径的约20％至约150％之间的目标直径的激光束在盲孔的外环内。在开口底部的称为“盲面”的表面包括通过激光钻孔形成的金属突起，使得金属突起与盲表面的一部分成一体。金属突起包括金属片的金属和来自电介质层的至少一个构成元件。然后蚀刻金属突起以形成与盲表面的一部分成一体的金属互锁结构。金属互锁结构包括分立的金属纤维，每个金属纤维具有弯曲（或卷曲）的几何形状。每种金属纤维具有其独特的组成，其包括金属，介电层的至少一个构成元件，或两者。

2. 发明授权

US06348737B1 Metallic interlocking structure 失效
标题翻译：形成金属互锁结构
公开(公告)号：US06348737B1
公开(公告)日：2002-02-19
申请号：US09517847
申请日：2000-03-02
申请人： Gerald G. Advocate, Jr. , Francis J. Downes, Jr. , Luis J. Matienzo , Ronald A. Kaschak , John S. Kresge , Daniel C. Van Hart
发明人： Gerald G. Advocate, Jr. , Francis J. Downes, Jr. , Luis J. Matienzo , Ronald A. Kaschak , John S. Kresge , Daniel C. Van Hart
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , H01L23/49827 , H01L2924/0002 , H05K3/0035 , H05K3/027 , H05K3/06 , H05K3/383 , H05K3/421 , H05K3/4644 , H05K2201/0248 , H05K2201/09509 , H05K2201/09563 , H05K2203/0307 , H05K2203/0353 , H01L2924/00
摘要： An electronic structure including a metallic interlocking structure for bonding a conductive plated layer to metal surface, and a method of forming the electronic structure. The method provides a substrate having a metallic sheet within a dielectric layer. The metallic sheet includes a metal such as copper. An opening in the substrate, such as a blind via, is formed by laser drilling through the dielectric layer and partially through the metallic sheet. If the opening is a blind via, then the laser drilling is within an outer ring of the blind via cross section using a laser beam having a target diameter between about 20% and about 150% of a radius of the blind via cross section. A surface at the bottom of the opening, called a “blind surface,” includes a metallic protrusion formed by the laser drilling, such that the metallic protrusion is integral with a portion of the blind surface. The metallic protrusion includes the metal of the metallic sheet and at least one constituent element from the dielectric layer. The metallic protrusion is then etched to form a metallic interlocking structure that is integral with the portion of the blind surface. The metallic interlocking structure includes discrete metallic fibers, with each metallic fiber having a curved (or curled) geometry. Each metallic fiber has its own unique composition that includes the metal, at least one constituent element of the dielectric layer, or both.
摘要翻译：一种电子结构，包括用于将导电镀层接合到金属表面的金属互锁结构，以及形成电子结构的方法。该方法提供了在电介质层内具有金属片的衬底。金属片包括铜等金属。通过激光钻孔穿过电介质层并且部分地穿过金属片，形成诸如盲孔之类的衬底中的开口。如果开口是盲孔，则激光钻孔是通过横截面的盲孔通过横截面的半径的约20％至约150％之间的目标直径的激光束在盲孔的外环内。在开口底部的称为“盲面”的表面包括通过激光钻孔形成的金属突起，使得金属突起与盲表面的一部分成一体。金属突起包括金属片的金属和来自电介质层的至少一个构成元件。然后蚀刻金属突起以形成与盲表面的一部分成一体的金属互锁结构。金属互锁结构包括分立的金属纤维，每个金属纤维具有弯曲（或卷曲）的几何形状。每种金属纤维具有其独特的组成，其包括金属，介电层的至少一个构成元件，或两者。

3. 发明授权

US06373717B1 Electronic package with high density interconnect layer 有权
公开(公告)号：US06373717B1
公开(公告)日：2002-04-16
申请号：US09540172
申请日：2000-03-31
申请人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
发明人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
IPC分类号： H05K118
CPC分类号： H05K3/4641 , H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

4. 发明授权

US06720502B1 Integrated circuit structure 有权
公开(公告)号：US06720502B1
公开(公告)日：2004-04-13
申请号：US09571611
申请日：2000-05-15
申请人： David J. Alcoe , Francis J. Downes, Jr. , Gerald W. Jones , John S. Kresge , Cheryl L. Tytran-Palomaki
发明人： David J. Alcoe , Francis J. Downes, Jr. , Gerald W. Jones , John S. Kresge , Cheryl L. Tytran-Palomaki
IPC分类号： H01R1204
CPC分类号： H01L23/49827 , H01L23/49822 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H05K3/4602 , H05K3/4641 , H05K2201/0215 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H01L2924/00
摘要： A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

5. 发明授权

US06887779B2 Integrated circuit structure 失效
标题翻译：集成电路结构
公开(公告)号：US06887779B2
公开(公告)日：2005-05-03
申请号：US10719495
申请日：2003-11-21
申请人： David J. Alcoe , Francis J. Downes, Jr. , Gerald W. Jones , John S. Kresge , Cheryl L. Tytran-Palomaki
发明人： David J. Alcoe , Francis J. Downes, Jr. , Gerald W. Jones , John S. Kresge , Cheryl L. Tytran-Palomaki
IPC分类号： H01L23/498 , H05K3/46 , H01L21/4763
CPC分类号： H01L23/49827 , H01L23/49822 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H05K3/4602 , H05K3/4641 , H05K2201/0215 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H01L2924/00
摘要： A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.
摘要翻译：一种具有增加的芯片连接器和电镀通孔密度的半导体芯片载体。特别地，其中具有多个电镀通孔的基板和其上的抗疲劳再分布层。再分配层包括选择性地定位在电镀通孔上并接触电镀通孔的多个通孔。所述基板还包括接地平面，两对信号面和两对电源层，其中所述第二对电源层位于所述外部电介质层的正下方。衬底内埋入电镀通孔。

6. 发明授权

US06829823B2 Method of making a multi-layered interconnect structure 有权
标题翻译：制造多层互连结构的方法
公开(公告)号：US06829823B2
公开(公告)日：2004-12-14
申请号：US10067551
申请日：2002-02-05
申请人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
发明人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
IPC分类号： H01K310
CPC分类号： H05K3/4641 , H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.
摘要翻译：一种制造多层互连结构的方法。第一和第二导电构件分别形成在第一和第二电介质层上。电介质层形成在导热层的相对表面上。第一和第二导电层形成在第一介电层内。第二导电层包括屏蔽信号导体并且位于第一导电层和导热层之间。通过互连结构形成的电镀通孔（PTH）电连接到第一和第二导电构件中的一个和屏蔽信号导体之一。形成在第一介电层上和第一导电构件的部分上的第三电介质层基本上覆盖在PTH上，并且包括用于提供从电子器件到屏蔽信号导体的电气路径的高密度互连层。

7. 发明授权

US08240027B2 Method of making circuitized substrates having film resistors as part thereof 失效
标题翻译：制造具有薄膜电阻器的电路化基板作为其一部分的方法
公开(公告)号：US08240027B2
公开(公告)日：2012-08-14
申请号：US12007820
申请日：2008-01-16
申请人： Frank D. Egitto , John S. Kresge , John M. Lauffer
发明人： Frank D. Egitto , John S. Kresge , John M. Lauffer
IPC分类号： H01C17/06 , H01C17/24 , H01C17/242
CPC分类号： H01C17/06 , H01C17/24 , H05K1/0268 , H05K1/167 , H05K2201/0355 , H05K2201/0969 , H05K2203/0361 , H05K2203/171 , Y10T29/49099 , Y10T29/49101
摘要： A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.
摘要翻译：一种制造电路化衬底的方法，其包括形成具有近似电阻值的多个单独的膜电阻器作为衬底的至少一个电路的一部分，测量代表性（样品）电阻器的电阻以限定其电阻，利用这些测量确定位于相对于代表性电阻器确定的接近度的其它剩余膜电阻器的对应精确宽度，使得这些剩余的膜电阻器将包括限定的电阻值，然后选择性地隔离这些剩余膜电阻器的电阻材料的限定部分，同时同时限定电阻材料的精确宽度，以使这些薄膜电阻器具有限定的电阻。

8. 发明申请

US20110284273A1 POWER CORE FOR USE IN CIRCUITIZED SUBSTRATE AND METHOD OF MAKING SAME 有权
标题翻译：在电路基板中使用的电源芯及其制造方法
公开(公告)号：US20110284273A1
公开(公告)日：2011-11-24
申请号：US12782187
申请日：2010-05-18
申请人： Robert M. Japp , Kostas Papathomas , John S. Kresge , Timothy Antesberger
发明人： Robert M. Japp , Kostas Papathomas , John S. Kresge , Timothy Antesberger
IPC分类号： H05K1/09 , H05K1/00 , H01R43/00 , H05K1/11
CPC分类号： H05K3/4641 , H05K3/4617 , H05K2201/068 , Y10T29/49117
摘要： A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.
摘要翻译：适于用作电路化基板（例如PCB或LCC）的一部分的电源核心。芯包括第一层低膨胀电介质和两个相邻的不同的低膨胀电介质结合的层，其中两个导电层位于两个添加的低膨胀介电层上。导电层中的至少一个用作功率芯的功率平面，而功率芯也可以在电路化的衬底内使用。还提供了制造电源芯和电路化基板的方法。使用不同的低膨胀电介质材料用于电源芯可以在一层中使用支撑增强玻璃纤维，而在其他两个电介质层中排除这种用途，从而防止形成在功率芯内的高度精确定义的通孔中的CAF短路问题。

9. 发明授权

US5620782A Method of fabricating a flex laminate package 失效
标题翻译：柔性层压包装的制造方法
公开(公告)号：US5620782A
公开(公告)日：1997-04-15
申请号：US459929
申请日：1995-06-02
申请人： Charles R. Davis , Thomas P. Duffy , Steven L. Hanakovic , Howard L. Heck , John T. Kolias , John S. Kresge , David N. Light , Ajit K. Trivedi
发明人： Charles R. Davis , Thomas P. Duffy , Steven L. Hanakovic , Howard L. Heck , John T. Kolias , John S. Kresge , David N. Light , Ajit K. Trivedi
IPC分类号： H01R4/26 , H01R4/58 , H01R12/61 , H01R13/66 , H05K1/00 , H05K1/03 , H05K1/14 , H05K3/00 , H05K3/32 , H05K3/46 , B32B9/00
CPC分类号： H05K3/4635 , H01R12/613 , H01R13/665 , H05K3/462 , H01R4/26 , H01R4/58 , H05K1/0373 , H05K1/0393 , H05K2201/015 , H05K2201/0154 , H05K2201/09109 , H05K2201/09536 , H05K2201/10159 , H05K3/328 , H05K3/4623 , H05K3/4641 , Y10S428/901 , Y10T29/49126 , Y10T29/49128 , Y10T29/49179 , Y10T428/24917
摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the per fluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the per fluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
摘要翻译：公开了一种并行处理器封装结构和用于制造该结构的方法。单独的逻辑和存储器元件在印刷电路卡上。这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。通过在层压板中实现的开关结构来提供互通。印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信，轴向电路（通孔和通孔）。各个子组件的层压是通过低熔点粘合剂来实现的，该低熔点粘合剂与要层压的区域中的子组件之间的每个碳氟化合物聚合物化学相容（可粘合），以及任选的与化学不相容的高熔点掩模不能粘合）在不想层压的区域中的子组件之间的每个碳氟聚合物。加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。

10. 发明授权

US5509196A Method of fabricating a flex laminate package 失效
标题翻译：柔性层压包装的制造方法
公开(公告)号：US5509196A
公开(公告)日：1996-04-23
申请号：US310190
申请日：1994-09-21
申请人： Charles R. Davis , Thomas P. Duffy , Steven L. Hanakovic , Howard L. Heck , John T. Kolias , John S. Kresge , David N. Light , Ajit K. Trivedi
发明人： Charles R. Davis , Thomas P. Duffy , Steven L. Hanakovic , Howard L. Heck , John T. Kolias , John S. Kresge , David N. Light , Ajit K. Trivedi
IPC分类号： H01R4/26 , H01R4/58 , H01R12/61 , H01R13/66 , H05K1/00 , H05K1/03 , H05K1/14 , H05K3/00 , H05K3/32 , H05K3/46 , H05K3/36 , H05K3/20
CPC分类号： H05K3/4635 , H01R12/613 , H01R13/665 , H05K3/462 , H01R4/26 , H01R4/58 , H05K1/0373 , H05K1/0393 , H05K2201/015 , H05K2201/0154 , H05K2201/09109 , H05K2201/09536 , H05K2201/10159 , H05K3/328 , H05K3/4623 , H05K3/4641 , Y10S428/901 , Y10T29/49126 , Y10T29/49128 , Y10T29/49179 , Y10T428/24917
摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
摘要翻译：公开了一种并行处理器封装结构和用于制造该结构的方法。单独的逻辑和存储器元件在印刷电路卡上。这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。通过在层压板中实现的开关结构来提供互通。电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。各个子组件的层压是通过与要层压的区域中的子组件之间的全氟化碳聚合物化学相容（可粘合）化学相容的低熔点粘合剂，以及任选的与化学不相容的高熔点掩模可粘合到）在不想层压的区域中的子组件之间的全氟化碳聚合物。加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。

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