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1. 发明授权

US08779554B2 MOSFETs with channels on nothing and methods for forming the same 有权
标题翻译：没有通道的MOSFET和用于形成通道的方法
公开(公告)号：US08779554B2
公开(公告)日：2014-07-15
申请号：US13436322
申请日：2012-03-30
申请人： Georgios Vellianitis , Mark van Dal , Blandine Duriez
发明人： Georgios Vellianitis , Mark van Dal , Blandine Duriez
IPC分类号： H01L29/06 , H01L29/778
CPC分类号： H01L21/76264 , H01L21/30604 , H01L21/764 , H01L29/0649 , H01L29/0653 , H01L29/1033 , H01L29/165 , H01L29/205 , H01L29/66477 , H01L29/66795 , H01L29/78 , H01L29/7853
摘要： A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.
摘要翻译：一种器件包括半导体衬底和半导体衬底上的晶体管的沟道区域。沟道区域包括半导体材料。气隙设置在通道区域的下方并与之对准，通道区域的底表面暴露于气隙。绝缘区域设置在气隙的相对侧上，其中沟道区域的底表面高于绝缘区域的顶表面。晶体管的栅极电介质设置在沟道区的顶表面和侧壁上。晶体管的栅电极在栅极电介质上方。

2. 发明申请

US20130256759A1 Fin Structure for a FinFET Device 有权
公开(公告)号：US20130256759A1
公开(公告)日：2013-10-03
申请号：US13431727
申请日：2012-03-27
申请人： Georgios Vellianitis , Mark van Dal , Blandine Duriez , Richard Oxland
发明人： Georgios Vellianitis , Mark van Dal , Blandine Duriez , Richard Oxland
IPC分类号： H01L29/12 , H01L21/20 , H01L27/088 , H01L29/02 , H01L29/165
CPC分类号： H01L29/41791 , H01L21/76224 , H01L21/76232 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/36 , H01L29/4236 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.

3. 发明授权

US08987835B2 FinFET with a buried semiconductor material between two fins 有权
标题翻译： FinFET在两个鳍片之间具有埋入的半导体材料
公开(公告)号：US08987835B2
公开(公告)日：2015-03-24
申请号：US13431727
申请日：2012-03-27
申请人： Georgios Vellianitis , Mark van Dal , Blandine Duriez , Richard Oxland
发明人： Georgios Vellianitis , Mark van Dal , Blandine Duriez , Richard Oxland
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/41791 , H01L21/76224 , H01L21/76232 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/36 , H01L29/4236 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.
摘要翻译：提供了一种鳍状场效应晶体管（FinFET）器件的鳍结构。该器件包括衬底，设置在衬底上的第一半导体材料，设置在衬底上并形成在第一半导体材料的相对侧上的浅沟槽隔离（STI）区域，以及形成第一鳍片和第二半导体材料的第二半导体材料翅片设置在STI区域上，第一鳍片与第二鳍片间隔开第一半导体材料的宽度。翅片结构可以用于通过形成在第一鳍片上形成的栅极层，设置在第一鳍片和第二鳍片之间的第一半导体材料的顶表面和第二鳍片来形成FinFET器件。

4. 发明申请

US20130256784A1 MOSFETs with Channels on Nothing and Methods for Forming the Same 有权
标题翻译：没有通道的MOSFET和其形成方法
公开(公告)号：US20130256784A1
公开(公告)日：2013-10-03
申请号：US13436322
申请日：2012-03-30
申请人： Georgios Vellianitis , Mark Van Dal , Blandine Duriez
发明人： Georgios Vellianitis , Mark Van Dal , Blandine Duriez
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76264 , H01L21/30604 , H01L21/764 , H01L29/0649 , H01L29/0653 , H01L29/1033 , H01L29/165 , H01L29/205 , H01L29/66477 , H01L29/66795 , H01L29/78 , H01L29/7853
摘要： A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.
摘要翻译：一种器件包括半导体衬底和半导体衬底上的晶体管的沟道区域。沟道区域包括半导体材料。气隙设置在通道区域的下方并与之对准，通道区域的底表面暴露于气隙。绝缘区域设置在气隙的相对侧上，其中沟道区域的底表面高于绝缘区域的顶表面。晶体管的栅极电介质设置在沟道区的顶表面和侧壁上。晶体管的栅电极在栅极电介质上方。

5. 发明授权

US09761666B2 Strained channel field effect transistor 有权
公开(公告)号：US09761666B2
公开(公告)日：2017-09-12
申请号：US13161649
申请日：2011-06-16
申请人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
发明人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
IPC分类号： H01L29/78 , H01L29/10 , H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/165
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823821 , H01L27/0924 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.

6. 发明申请

US20120319211A1 STRAINED CHANNEL FIELD EFFECT TRANSISTOR 有权
标题翻译：应变通道场效应晶体管
公开(公告)号：US20120319211A1
公开(公告)日：2012-12-20
申请号：US13161649
申请日：2011-06-16
申请人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
发明人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823821 , H01L27/0924 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.
摘要翻译：本公开提供了具有应变SiGe沟道的半导体器件和制造这种器件的方法。在一个实施例中，半导体器件包括包括至少两个隔离特征的衬底，设置在至少两个隔离特征之间和之上的散热片衬底以及设置在散热片衬底的暴露部分之上的外延层。根据一个方面，外延层可以设置在翅片衬底的顶表面和侧壁上。根据另一方面，翅片基板可以基本上完全设置在至少两个隔离特征之上。

7. 发明申请

US20120228717A1 SCHOTTKY DIODE AND METHOD OF MANUFACTURE 有权
标题翻译：肖特基二极管及其制造方法
公开(公告)号：US20120228717A1
公开(公告)日：2012-09-13
申请号：US13500405
申请日：2010-11-17
申请人： Georgios Vellianitis , Gilberto Curatola , Kyriaki Fotopoulou , Nader Akil
发明人： Georgios Vellianitis , Gilberto Curatola , Kyriaki Fotopoulou , Nader Akil
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0629 , H01L27/0814 , H01L27/095 , H01L29/66143 , H01L29/872
摘要： A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells (16) for forming CMOS devices and second wells (18) for forming Schottky devices. Then, transistors arc formed in the first wells, the second wells protected with a protection layer (20) and suicide contacts (40) formed to source and drain regions in the first wells. The protection layer is then removed, a Schottky material deposited and etched away except in a contact region in each second well to form a Schottky contact between the Schottky material (74) and each second well (18).
摘要翻译：在CMOS工艺中制造肖特基二极管的方法包括形成阱，包括用于形成CMOS器件的第一阱（16）和用于形成肖特基器件的第二阱（18）。然后，在第一阱中形成晶体管，第二阱由保护层（20）和形成于第一阱中的源极和漏极区域的硅化物触点（40）保护。然后去除保护层，除了在每个第二阱中的接触区域中沉积并蚀刻掉肖特基材料，以在肖特基材料（74）和每个第二阱（18）之间形成肖特基接触。

8. 发明授权

US08119494B1 Defect-free hetero-epitaxy of lattice mismatched semiconductors 有权
标题翻译：晶格失配半导体的无缺陷异质外延
公开(公告)号：US08119494B1
公开(公告)日：2012-02-21
申请号：US12846307
申请日：2010-07-29
申请人： Georgios Vellianitis
发明人： Georgios Vellianitis
IPC分类号： H01L21/76 , H01L21/36
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0245 , H01L21/02455 , H01L21/02532 , H01L21/02639 , H01L21/02647
摘要： A method includes providing a semiconductor substrate formed of a first semiconductor material; and forming a plurality of insulation regions over at least a portion of the semiconductor substrate, with a plurality of trenches separating the plurality of insulation regions apart from each other. A first epitaxial growth is performed to epitaxially grow a plurality of semiconductor regions in the plurality of trenches, wherein (111) facets are formed and exposed during the step of the first epitaxial growth. When the (111) facets of neighboring ones of the plurality of semiconductor regions touch each other, a second epitaxial growth is performed to continue grow the plurality of semiconductor regions to form (100) planes between the neighboring ones of the plurality of semiconductor regions.
摘要翻译：一种方法包括提供由第一半导体材料形成的半导体衬底; 以及在所述半导体衬底的至少一部分上形成多个绝缘区域，多个沟槽将所述多个绝缘区域彼此分开。进行第一外延生长以外延生长多个沟槽中的多个半导体区域，其中（111）面在第一外延生长步骤期间形成和暴露。当多个半导体区域中相邻的半导体区域的（111）面彼此接触时，执行第二外延生长以继续生长多个半导体区域以在多个半导体区域中的相邻半导体区域之间形成（100）平面。

9. 发明申请

US20120028444A1 DEFECT-FREE HETERO-EPITAXY OF LATTICE MISMATCHED SEMICONDUCTORS 有权
标题翻译：无缺陷异质结构的绝缘失配半导体
公开(公告)号：US20120028444A1
公开(公告)日：2012-02-02
申请号：US12846307
申请日：2010-07-29
申请人： Georgios Vellianitis
发明人： Georgios Vellianitis
IPC分类号： H01L21/20
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0245 , H01L21/02455 , H01L21/02532 , H01L21/02639 , H01L21/02647
摘要： A method includes providing a semiconductor substrate formed of a first semiconductor material; and forming a plurality of insulation regions over at least a portion of the semiconductor substrate, with a plurality of trenches separating the plurality of insulation regions apart from each other. A first epitaxial growth is performed to epitaxially grow a plurality of semiconductor regions in the plurality of trenches, wherein (111) facets are formed and exposed during the step of the first epitaxial growth. When the (111) facets of neighboring ones of the plurality of semiconductor regions touch each other, a second epitaxial growth is performed to continue grow the plurality of semiconductor regions to form (100) planes between the neighboring ones of the plurality of semiconductor regions.
摘要翻译：一种方法包括提供由第一半导体材料形成的半导体衬底; 以及在所述半导体衬底的至少一部分上形成多个绝缘区域，多个沟槽将所述多个绝缘区域彼此分开。进行第一外延生长以外延生长多个沟槽中的多个半导体区域，其中（111）面在第一外延生长步骤期间形成和暴露。当多个半导体区域中相邻的半导体区域的（111）面彼此接触时，执行第二外延生长以继续生长多个半导体区域以在多个半导体区域中的相邻半导体区域之间形成（100）平面。

10. 发明授权

US08709885B2 Schottky diode and method of manufacture 有权
标题翻译：肖特基二极管及其制造方法
公开(公告)号：US08709885B2
公开(公告)日：2014-04-29
申请号：US13500405
申请日：2010-11-17
申请人： Georgios Vellianitis , Gilberto Curatola , Kyriaki Fotopoulou , Nader Akil
发明人： Georgios Vellianitis , Gilberto Curatola , Kyriaki Fotopoulou , Nader Akil
IPC分类号： H01L21/338
CPC分类号： H01L27/0629 , H01L27/0814 , H01L27/095 , H01L29/66143 , H01L29/872
摘要： A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells (16) for forming CMOS devices and second wells (18) for forming Schottky devices. Then, transistors are formed in the first wells, the second wells protected with a protection layer (20) and suicide contacts (40) formed to source and drain regions in the first wells. The protection layer is then removed, a Schottky material deposited and etched away except in a contact region in each second well to form a Schottky contact between the Schottky material (74) and each second well (18).
摘要翻译：在CMOS工艺中制造肖特基二极管的方法包括形成阱，包括用于形成CMOS器件的第一阱（16）和用于形成肖特基器件的第二阱（18）。然后，晶体管形成在第一阱中，第二阱由保护层（20）和形成于第一阱中的源极和漏极区域的硅化物接触（40）保护。然后去除保护层，除了在每个第二阱中的接触区域中沉积并蚀刻掉肖特基材料，以在肖特基材料（74）和每个第二阱（18）之间形成肖特基接触。

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