专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120319211A1 STRAINED CHANNEL FIELD EFFECT TRANSISTOR 有权
标题翻译：应变通道场效应晶体管
公开(公告)号：US20120319211A1
公开(公告)日：2012-12-20
申请号：US13161649
申请日：2011-06-16
申请人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
发明人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823821 , H01L27/0924 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.
摘要翻译：本公开提供了具有应变SiGe沟道的半导体器件和制造这种器件的方法。在一个实施例中，半导体器件包括包括至少两个隔离特征的衬底，设置在至少两个隔离特征之间和之上的散热片衬底以及设置在散热片衬底的暴露部分之上的外延层。根据一个方面，外延层可以设置在翅片衬底的顶表面和侧壁上。根据另一方面，翅片基板可以基本上完全设置在至少两个隔离特征之上。

2. 发明授权

US09761666B2 Strained channel field effect transistor 有权
公开(公告)号：US09761666B2
公开(公告)日：2017-09-12
申请号：US13161649
申请日：2011-06-16
申请人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
发明人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
IPC分类号： H01L29/78 , H01L29/10 , H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/165
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823821 , H01L27/0924 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.

3. 发明授权

US08766364B2 Fin field effect transistor layout for stress optimization 有权
标题翻译： Fin场效应晶体管布局用于应力优化
公开(公告)号：US08766364B2
公开(公告)日：2014-07-01
申请号：US13600369
申请日：2012-08-31
申请人： Gerben Doornbos , Mark van Dal
发明人： Gerben Doornbos , Mark van Dal
IPC分类号： H01L27/12
CPC分类号： H01L27/0207 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/7843
摘要： The present disclosure describes a layout for stress optimization. The layout includes a substrate, at least two fin field effect transistors (FinFET) cells formed in the substrate, a FinFET fin designed to cross the two FinFET cells, a plurality of gates formed on the substrate, and an isolation unit formed between the first FinFET cell and the second FinFET cell. The two FinFET cells include a first FinFET cell and a second FinFET cell. The FinFET fin includes a positive charge FinFET (Fin PFET) fin and a negative charge FinFET (Fin NFET) fin. The isolation unit isolates the first FinFET cell from the second FinFET cell without breaking the FinFET fin.
摘要翻译：本公开描述了用于应力优化的布局。该布局包括衬底，在衬底中形成的至少两个鳍状场效应晶体管（FinFET）单元，设计成跨过两个FinFET单元的FinFET鳍，形成在衬底上的多个栅极，以及形成在第一 FinFET单元和第二个FinFET单元。两个FinFET单元包括第一FinFET单元和第二FinFET单元。 FinFET鳍片包括正电荷FinFET（Fin PFET）鳍和负电荷FinFET（Fin NFET）鳍。隔离单元将第一FinFET单元与第二FinFET单元隔离，而不会破坏FinFET鳍。

4. 发明申请

US20140061801A1 FIN FIELD EFFECT TRANSISTOR LAYOUT FOR STRESS OPTIMIZATION 有权
标题翻译：用于应力优化的FIN场效应晶体管布局
公开(公告)号：US20140061801A1
公开(公告)日：2014-03-06
申请号：US13600369
申请日：2012-08-31
申请人： Gerben Doornbos , Mark van Dal
发明人： Gerben Doornbos , Mark van Dal
IPC分类号： H01L27/12
CPC分类号： H01L27/0207 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/7843
摘要： The present disclosure describes a layout for stress optimization. The layout includes a substrate, at least two fin field effect transistors (FinFET) cells formed in the substrate, a FinFET fin designed to cross the two FinFET cells, a plurality of gates formed on the substrate, and an isolation unit formed between the first FinFET cell and the second FinFET cell. The two FinFET cells include a first FinFET cell and a second FinFET cell. The FinFET fin includes a positive charge FinFET (Fin PFET) fin and a negative charge FinFET (Fin NFET) fin. The isolation unit isolates the first FinFET cell from the second FinFET cell without breaking the FinFET fin.
摘要翻译：本公开描述了用于应力优化的布局。该布局包括衬底，在衬底中形成的至少两个鳍状场效应晶体管（FinFET）单元，设计成跨过两个FinFET单元的FinFET鳍，形成在衬底上的多个栅极，以及形成在第一 FinFET单元和第二个FinFET单元。两个FinFET单元包括第一FinFET单元和第二FinFET单元。 FinFET鳍片包括正电荷FinFET（Fin PFET）鳍和负电荷FinFET（Fin NFET）鳍。隔离单元将第一FinFET单元与第二FinFET单元隔离，而不会破坏FinFET鳍。

5. 发明授权

US08148052B2 Double patterning for lithography to increase feature spatial density 有权
标题翻译：用于光刻的双重图案化以增加特征空间密度
公开(公告)号：US08148052B2
公开(公告)日：2012-04-03
申请号：US12514777
申请日：2007-11-13
申请人： Anja Monique Vanleenhove , Peter Dirksen , David Van Steenwinckel , Gerben Doornbos , Casper Juffermans , Mark Van Dal
发明人： Anja Monique Vanleenhove , Peter Dirksen , David Van Steenwinckel , Gerben Doornbos , Casper Juffermans , Mark Van Dal
IPC分类号： G03F7/26
CPC分类号： G03F7/0035 , G03F7/11 , H01L21/0271 , H01L21/0273 , H01L21/823821 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.
摘要翻译：在衬底中或衬底上的至少一个器件层中形成图案的方法包括：用第一光致抗蚀剂层涂覆器件层; 使用第一掩模曝光第一光致抗蚀剂; 显影第一光致抗蚀剂层以在基底上形成第一图案; 用保护层涂覆基板; 处理保护层以在其中与第一光致抗蚀剂接触的地方发生变化，使得改变的保护层基本上不受随后的曝光和/或显影步骤的影响; 用第二光致抗蚀剂层涂覆基板; 使用第二掩模曝光所述第二光致抗蚀剂层; 并且显影所述第二光致抗蚀剂层以在所述基板上形成第二图案，而不会显着影响所述第一光致抗蚀剂层中的所述第一图案，其中所述第一和第二图案一起限定散布特征，其空间频率大于第一和第二模式分开。该方法在定义具有较小的特征尺寸的finFET器件的源极，漏极和鳍片特征方面具有特别的用途，而与主要的光刻工具不同。

6. 发明申请

US20100028809A1 DOUBLE PATTERNING FOR LITHOGRAPHY TO INCREASE FEATURE SPATIAL DENSITY 有权
标题翻译：用于提升特征空间密度的双重图案
公开(公告)号：US20100028809A1
公开(公告)日：2010-02-04
申请号：US12514777
申请日：2007-11-13
申请人： Anja Monique Vanleenhove , Peter Dirksen , David Van Steenwinckel , Gerben Doornbos , Casper Juffermans , Mark Van Dal
发明人： Anja Monique Vanleenhove , Peter Dirksen , David Van Steenwinckel , Gerben Doornbos , Casper Juffermans , Mark Van Dal
IPC分类号： G03F7/20
CPC分类号： G03F7/0035 , G03F7/11 , H01L21/0271 , H01L21/0273 , H01L21/823821 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spartial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.
摘要翻译：在衬底中或衬底上的至少一个器件层中形成图案的方法包括：用第一光致抗蚀剂层涂覆器件层; 使用第一掩模曝光第一光致抗蚀剂; 显影第一光致抗蚀剂层以在基底上形成第一图案; 用保护层涂覆基板; 处理保护层以在其中与第一光致抗蚀剂接触的地方发生变化，使得改变的保护层基本上不受随后的曝光和/或显影步骤的影响; 用第二光致抗蚀剂层涂覆基板; 使用第二掩模曝光所述第二光致抗蚀剂层; 并且显影所述第二光致抗蚀剂层以在所述衬底上形成第二图案，而不会显着影响所述第一光致抗蚀剂层中的所述第一图案，其中所述第一和第二图案一起限定散布特征，其间隔频率大于每个第一和第二模式分开。该方法在定义具有较小的特征尺寸的finFET器件的源极，漏极和鳍片特征方面具有特别的用途，而与主要的光刻工具不同。

7. 发明授权

US08916927B2 Vertical tunnel field effect transistor (FET) 有权
标题翻译：垂直隧道场效应晶体管（FET）
公开(公告)号：US08916927B2
公开(公告)日：2014-12-23
申请号：US13553405
申请日：2012-07-19
申请人： Krishna Bhuwalka , Gerben Doornbos , Matthias Passlack
发明人： Krishna Bhuwalka , Gerben Doornbos , Matthias Passlack
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/66977 , B82Y10/00 , H01L29/0657 , H01L29/0676 , H01L29/068 , H01L29/0688 , H01L29/1037 , H01L29/1054 , H01L29/205 , H01L29/42372 , H01L29/66356 , H01L29/66439 , H01L29/66522 , H01L29/66666 , H01L29/7391 , H01L29/775 , H01L29/7827
摘要： Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.
摘要翻译：除此之外，本文提供了用于形成垂直隧道场效应晶体管（FET）的一种或多种技术以及所产生的垂直隧道FET。在一个实施例中，垂直隧道FET通过在第一类型的衬底区域上形成芯体形成，围绕围绕圆周的圆周形成第二类型沟道壳体，围绕围绕圆周的圆周形成栅极电介质，形成围绕圆周大于芯圆周的栅电极，并且在第二类型沟槽壳体的一部分上形成第二类型区域，其中第二类型具有与第一类型的掺杂相反的掺杂。以这种方式，能够进行线路隧道，从而为垂直隧道FET提供增强的隧道效率。

8. 发明授权

US08604518B2 Split-channel transistor and methods for forming the same 有权
标题翻译：分裂沟道晶体管及其形成方法
公开(公告)号：US08604518B2
公开(公告)日：2013-12-10
申请号：US13307738
申请日：2011-11-30
申请人： Krishna Kumar Bhuwalka , Gerben Doornbos , Matthias Passlack
发明人： Krishna Kumar Bhuwalka , Gerben Doornbos , Matthias Passlack
IPC分类号： H01L29/66
CPC分类号： H01L29/66431 , H01L29/1054 , H01L29/205 , H01L29/267 , H01L29/66522 , H01L29/66795 , H01L29/785
摘要： A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel.
摘要翻译：鳍场效应晶体管（FinFET）包括鳍，其包括具有第一带隙的沟道分离器和包括在沟道分离器的相对侧壁上的第一部分和第二部分的沟道。通道具有小于第一带隙的第二带隙。栅极电极包括在鳍片的相对侧上的第一部分和第二部分。栅极绝缘体包括位于栅极电极的第一部分和沟道的第一部分之间的第一部分，以及栅电极的第二部分和沟道的第二部分之间的第二部分。

9. 发明申请

US20090114950A1 Semiconductor Device and Method of Manufacturing such a Device 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090114950A1
公开(公告)日：2009-05-07
申请号：US11597533
申请日：2005-05-19
申请人： Prabhat Agarwal , Jan Willem Slotboom , Gerben Doornbos
发明人： Prabhat Agarwal , Jan Willem Slotboom , Gerben Doornbos
IPC分类号： H01L21/336 , H01L21/8249 , H01L21/8232 , H01L29/78 , H01L29/80 , H01L21/8234 , H01L21/8248
CPC分类号： H01L21/8249
摘要： The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with—interposed between said source and drain regions—a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2). According to the invention, the semiconductor body (1) is provided not only with the field effect transistor (M) but also with a bipolar transistor (B) with emitter, base and collector regions (5A, 5B, 5C) of respectively the second, the first and the second conductivity type, and the emitter region (5A) is formed in the second semiconductor layer (3) and the base region (5B) is formed in the first semiconductor layer (2). In this way a Bi(C)MOS IC (10) is obtained which is very suitable for high-frequency applications and which is easy to manufacture using a method according to the invention. Preferably the first semiconductor layer (2) comprises Si—Ge and is delta-doped, whereas the second semiconductor layer (3) comprises strained Si.
摘要翻译：本发明涉及一种半导体器件（10），它包括具有半导体层结构的硅衬底（12）和半导体本体（1），半导体层结构依次包括第一和第二半导体层（2,3），并且具有具有与第一导电类型相反的具有第二导电类型的沟道的场效应晶体管（M）的第一导电类型的表面区域，其中所述表面区域设置有源极和漏极区域（4A，4B））和用于场效应晶体管（M）的第二导电类型，并且插入在所述源极和漏极区之间 - 具有较低掺杂浓度的沟道区（3A），其形成第二半导体层（3）的一部分，并且具有埋入第一导电型半导体区域（2A），其掺杂在沟道区域（3A）的下方，掺杂浓度比沟道区域（3A）的掺杂浓度高得多，并且形成第一半导体层（2）的一部分，。根据本发明，半导体本体（1）不仅设置有场效应晶体管（M），而且还具有双极晶体管（B），发射极，基极和集电极区域（5A，5B，5C）分别为第二第一和第二导电类型和发射极区域（5A）形成在第二半导体层（3）中，并且基极区域（5B）形成在第一半导体层（2）中。以这种方式获得了非常适合于高频应用并且易于使用根据本发明的方法制造的Bi（C）MOS IC（10）。优选地，第一半导体层（2）包括Si-Ge并且是δ掺杂的，而第二半导体层（3）包括应变Si。

10. 发明授权

US09735239B2 Semiconductor device channel system and method 有权
公开(公告)号：US09735239B2
公开(公告)日：2017-08-15
申请号：US13444695
申请日：2012-04-11
申请人： Gerben Doornbos , Krishna Kumar Bhuwalka , Matthias Passlack
发明人： Gerben Doornbos , Krishna Kumar Bhuwalka , Matthias Passlack
IPC分类号： H01L29/66 , H01L29/205 , H01L29/10 , H01L29/78
CPC分类号： H01L29/205 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式