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    • 4. 发明授权
    • Systems and methods for equalizer optimization in a storage access retry
    • 存储访问重试中均衡器优化的系统和方法
    • US07948699B2
    • 2011-05-24
    • US12348236
    • 2009-01-02
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • G11B5/09
    • G11B20/10009G11B20/10046G11B20/10055G11B20/10481G11B20/18G11B2020/183G11B2220/2516
    • Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
    • 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。
    • 5. 发明申请
    • Systems and Methods for Equalizer Optimization in a Storage Access Retry
    • 存储访问重试中均衡器优化的系统和方法
    • US20100172046A1
    • 2010-07-08
    • US12348236
    • 2009-01-02
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • G11B20/10
    • G11B20/10009G11B20/10046G11B20/10055G11B20/10481G11B20/18G11B2020/183G11B2220/2516
    • Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
    • 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。
    • 8. 发明申请
    • FLY-HEIGHT CONTROL USING ASYNCHRONOUS SAMPLING
    • 使用异步采样的飞行高度控制
    • US20110249361A1
    • 2011-10-13
    • US12758122
    • 2010-04-12
    • George MathewJeffrey GrundvigHongwei SongYuan Xing Lee
    • George MathewJeffrey GrundvigHongwei SongYuan Xing Lee
    • G11B21/02
    • G11B5/6029G11B5/012G11B5/6064
    • In one embodiment, a hard-disk drive system performs fly-height control using a read-back mode and a loop-back mode. The read-back mode measures first and second harmonics pre-recorded on the medium and divides the first measurement by the second to obtain a read-back mode harmonic ratio. The loop-back mode measures the same first and second harmonics; however, the harmonics are provided by a write precompensation circuit rather than the medium. Further, the loop-back mode measurements are performed using asynchronous sampling to address aliasing and quantization errors. The first measurement is divided by the second to generate a loop-back harmonic ratio. In logarithm domain, the loop-back ratio is subtracted from the read-back mode ratio to remove environment-induced variations in the read path electronic circuits. The resulting harmonic ratio is subtracted from an initial harmonic ratio determined, for example, during manufacturing, to determine how much the harmonic ratio has changed.
    • 在一个实施例中,硬盘驱动器系统使用回读模式和循环模式来执行飞行高度控制。 回读模式测量在介质上预先记录的第一和第二次谐波,并将第一次测量除以秒,以获得回读模式谐波比。 环回模式测量相同的第一和第二谐波; 然而,谐波由写入预补偿电路而不是介质提供。 此外,使用异步采样来执行环回模式测量以解决混叠和量化误差。 第一次测量除以二次以产生回路谐波比。 在对数域中,从回读模式比率中减去回路比,以消除读取路径电子电路中的环境引起的变化。 从制造时例如确定的初始谐波比减去得到的谐波比,以确定谐波比已经改变了多少。
    • 9. 发明申请
    • Systems and Methods for Adaptive CBD Estimation in a Storage Device
    • 存储设备中自适应CBD估计的系统和方法
    • US20100182718A1
    • 2010-07-22
    • US12663345
    • 2008-10-20
    • George MathewYuan Xing LeeHongwei SongJefferson E. Singleton
    • George MathewYuan Xing LeeHongwei SongJefferson E. Singleton
    • G11B21/02
    • G11B5/6029
    • Various embodiments of the present invention provide systems and methods for adaptive channel bit density estimation. For example, various embodiments of the present invention provide methods for adaptively estimating channel bit density. Such methods include providing a storage medium (178) that includes information corresponding to a process data set, and accessing the process data set from the storage medium (505). A first channel bit density estimate (535) is computed based at least in part on a first portion of the process data set (520-530), and a second channel bit density estimate (535) is calculated based at least in part on the first portion of the process data set, a second portion of the process data set (520-530) and the first channel bit density estimate (535).
    • 本发明的各种实施例提供了用于自适应信道比特密度估计的系统和方法。 例如,本发明的各种实施例提供了自适应地估计信道比特密度的方法。 这样的方法包括提供包括与过程数据集相对应的信息的存储介质(178),以及从存储介质(505)访问过程数据集。 至少部分地基于过程数据集(520-530)的第一部分来计算第一信道比特密度估计(535),并且至少部分地基于所述第二信道比特密度估计 过程数据集的第一部分,过程数据集(520-530)的第二部分和第一信道比特密度估计(535)。
    • 10. 发明申请
    • Systems and Methods for Dibit Correction
    • Dibit校正系统与方法
    • US20100157458A1
    • 2010-06-24
    • US12463626
    • 2009-05-11
    • George MathewHongwei SongYuan Xing Lee
    • George MathewHongwei SongYuan Xing Lee
    • G11B20/10
    • G11B20/10203G11B2220/2516
    • Various embodiments of the present invention provide systems and methods for providing a corrected dibit signal. As an example, various embodiments of the present invention provide dibit correction circuits. Such dibit correction circuits include a dibit sample buffer, a maximum sample detector circuit, a side sample detector circuit, and a dibit correction circuit. The dibit sample buffer includes a plurality of samples of an uncorrected dibit signal. The maximum sample detector circuit identifies a maximum sample of the plurality of samples of the uncorrected dibit signal, and the side sample detector circuit identifies a first side sample prior to the maximum sample on the uncorrected dibit signal and a second side sample following the maximum sample on the uncorrected dibit signal. The dibit correction circuit applies a correction factor calculated based at least in part on the maximum sample, the first side sample and the second side sample to at least a subset of the plurality of samples of the uncorrected dibit signals to yield a plurality of corrected dibit signals.
    • 本发明的各种实施例提供了用于提供校正的双位信号的系统和方法。 作为示例,本发明的各种实施例提供双向校正电路。 这种二进制校正电路包括二进制采样缓冲器,最大采样检测器电路,侧样本检测器电路和二位校正电路。 双位采样缓冲器包括多个未校正的双位信号的样本。 最大样本检测器电路识别未校正的双位信号的多个样本的最大样本,并且侧样本检测器电路识别在未校正的双位信号上的最大样本之前的第一侧样本,以及最大样本之后的第二侧样本 对未校正的双位信号。 双向校正电路将至少部分地基于最大采样,第一侧采样和第二侧采样计算的校正因子应用于未校正的双位信号的多个采样的至少一个子集,以产生多个校正的双位 信号。