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1. 发明授权

US6030881A High throughput chemical vapor deposition process capable of filling high aspect ratio structures 失效
标题翻译：能够填充高纵横比结构的高通量化学气相沉积工艺
公开(公告)号：US6030881A
公开(公告)日：2000-02-29
申请号：US72759
申请日：1998-05-05
申请人： George D. Papasouliotis , Ashima B. Chakravarti , Richard A. Conti , Laertis Economikos , Patrick A. Van Cleemput
发明人： George D. Papasouliotis , Ashima B. Chakravarti , Richard A. Conti , Laertis Economikos , Patrick A. Van Cleemput
IPC分类号： C23C16/04 , C23C16/40 , C23C16/56 , H01L21/762
CPC分类号： H01L21/76224 , C23C16/045 , C23C16/401 , C23C16/56
摘要： A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.
摘要翻译：提供了一种通过使用具有不同蚀刻速率 - 沉积速率（蚀刻/去除）比率的沉积和蚀刻步骤顺序的高密度等离子体（HDP）沉积工艺来填充高纵横比间隙而无空隙形成的方法。第一步使用小于1的蚀刻/剥离比快速填充间隙。第一步在打开间隙之前中断。第二步使用大于1的蚀刻/剥离比来扩大间隙。在形成间隙的元件的角部暴露之前停止第二步骤。可以重复这些步骤，直到间隙的纵横比减小，使得无空隙间隙填充成为可能。可以优化每个步骤的蚀刻/剥离比和持续时间，以实现高通量和高纵横比填充间隙。

2. 发明授权

US06429149B1 Low temperature LPCVD PSG/BPSG process 失效
标题翻译：低温LPCVD PSG / BPSG工艺
公开(公告)号：US06429149B1
公开(公告)日：2002-08-06
申请号：US09511394
申请日：2000-02-23
申请人： Ashima B. Chakravarti , Richard A. Conti , Laertis Economikos , Byeongju Park
发明人： Ashima B. Chakravarti , Richard A. Conti , Laertis Economikos , Byeongju Park
IPC分类号： H01L2131
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02129 , H01L21/02164 , H01L21/02337 , H01L21/31625
摘要： A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.
摘要翻译：所公开的方法使用在衬底上的掺杂氧化物膜的低压化学气相沉积（LPCVD）。该方法包括以下步骤：在LPCVD反应器中提供衬底并将BTBAS和氧气流入LPCVD反应器以在衬底上反应以在衬底上沉积氧化物膜。掺杂的前体流入LPCVD反应器以在氧化膜沉积在衬底上时掺杂氧化膜。该方法在相对低的LPCVD反应温度下产生掺杂的氧化物膜。

3. 发明授权

US06500772B2 Methods and materials for depositing films on semiconductor substrates 失效
标题翻译：用于在半导体衬底上沉积膜的方法和材料
公开(公告)号：US06500772B2
公开(公告)日：2002-12-31
申请号：US09757072
申请日：2001-01-08
申请人： Ashima B. Chakravarti , Richard A. Conti , Chester Dziobkowski , Thomas Ivers , Paul Jamison , Frank Liucci
发明人： Ashima B. Chakravarti , Richard A. Conti , Chester Dziobkowski , Thomas Ivers , Paul Jamison , Frank Liucci
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , C23C16/30 , H01L21/02167 , H01L21/02222 , H01L21/02274 , H01L21/0332 , H01L21/3145 , H01L21/31608 , H01L21/3185
摘要： A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.
摘要翻译：一种在衬底上沉积膜的方法，包括在存在等离子体能量的情况下放置衬底，并使衬底与包含式（R-NH）4-nSiXn的化合物的反应性气体组分接触，其中R是烷基基团，n为1,2或3，并且X选自氢或卤素。反应性气体组合物还可以包含氧化剂和/或还原剂。

4. 发明授权

US6159870A Borophosphosilicate glass incorporated with fluorine for low thermal budget gap fill 失效
标题翻译：掺有氟的硼磷硅玻璃用于低热量预算缺口填充
公开(公告)号：US6159870A
公开(公告)日：2000-12-12
申请号：US210411
申请日：1998-12-11
申请人： Ashima B. Chakravarti , Richard A. Conti , Frank V. Liucci , Darryl D. Restaino
发明人： Ashima B. Chakravarti , Richard A. Conti , Frank V. Liucci , Darryl D. Restaino
IPC分类号： H01L21/20 , H01L21/316 , H01L21/31 , H01L21/469
CPC分类号： H01L21/31604 , H01L21/31625 , H01L21/31629
摘要： A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480.degree. C. at sub-atmospheric pressures of about 200 Torr. Preferably, gaseous reactants used in the method comprise TEOS, FTES, TEPO and TEB with an ozone/oxygen mixture. Dopant concentrations of boron and phosphorus are sufficiently low such that surface crystallite defects and hygroscopicity are avoided. The as-deposited films at lower aspect ratio gaps are substantially void-free such that subsequent anneal of the film is not required. Films deposited into higher aspect ratio gaps are annealed at or below about 750.degree. C., well within the thermal budget for most DRAM, logic and merged logic-DRAM chips. The resultant FBPSG layer contains less than or equal to about 5.0 wt % boron, less than about 4.0 wt % phosphorus, and about 0.1 to 2.0 wt % fluorine.
摘要翻译：在半导体器件上沉积氟化硼磷硅酸盐玻璃（FBPSG）作为最终或层间绝缘膜的方法。纵横比大于6:1的间隙在约200托的亚大气压下，在约480℃的温度下填充基本上无空隙的FBPSG膜。优选地，在该方法中使用的气态反应物包括具有臭氧/氧混合物的TEOS，FTES，TEPO和TEB。硼和磷的掺杂浓度足够低，从而避免表面微晶缺陷和吸湿性。较低纵横比间隙的沉积膜基本上无空隙，使得不需要膜的后续退火。沉积在较高纵横比间隙中的膜在大约750℃或更低温度下退火，完全在大多数DRAM，逻辑和合并逻辑DRAM芯片的热预算内。所得的FBPSG层含有小于或等于约5.0重量％的硼，小于约4.0重量％的磷和约0.1至2.0重量％的氟。

5. 发明授权

US6077786A Methods and apparatus for filling high aspect ratio structures with silicate glass 失效
标题翻译：用硅酸盐玻璃填充高纵横比结构的方法和装置
公开(公告)号：US6077786A
公开(公告)日：2000-06-20
申请号：US854011
申请日：1997-05-08
申请人： Ashima B. Chakravarti , Richard A. Conti , Donna R. Cote , Frank V. Liucci , Son V. Nguyen
发明人： Ashima B. Chakravarti , Richard A. Conti , Donna R. Cote , Frank V. Liucci , Son V. Nguyen
IPC分类号： H01L21/316 , H01L21/762 , H01L21/311
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/02131 , H01L21/02164 , H01L21/02271 , H01L21/31625 , H01L21/76224
摘要： Filling of narrow and/or high aspect ratio gaps and trenches with silicate glass is accomplished at reduced temperatures and without reflow by etching the glass concurrently with thermal chemical vapor deposition of the glass such that the deposition rate will exceed the etching rate by a relatively small net deposition rate near the surface with the excess deposition rate increasing over the depth of the trench or gap. The as-deposited glass film is made dense and stable by carrying out the concurrent etch and deposition process at an elevated temperature but which is within the maximum temperature and heat budget which can be tolerated by structures formed by previously performed processes. Fluorine can be incorporated in the silicate glass film as a dopant in sufficient concentration to reduce dielectric constant of the film. Phosphorus and/or boron can be incorporated into the film, as well, and may enhance void-free filling of trenches and gaps.
摘要翻译：使用硅酸盐玻璃填充窄和/或高长宽比的间隙和沟槽在降低的温度下完成，并且通过在玻璃的热化学气相沉积中同时蚀刻玻璃而不进行回流，使得沉积速率将超过蚀刻速率相对较小表面附近的净沉积速率随着沟槽或间隙的深度而增加。通过在升高的温度下进行同时蚀刻和沉积工艺，但是在由先前执行的工艺形成的结构可以容忍的最大温度和热量预算范围内，将沉积的玻璃膜制成致密和稳定的。氟可以以足够的浓度掺入到硅酸盐玻璃膜中作为掺杂剂以降低膜的介电常数。也可以将磷和/或硼掺入到膜中，并且可以增强沟槽和间隙的无空隙填充。

6. 发明授权

US08575655B2 Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering 有权
标题翻译：具有高K金属栅极集成和SiGe沟道工程的PMOS器件的方法和结构
公开(公告)号：US08575655B2
公开(公告)日：2013-11-05
申请号：US13431328
申请日：2012-03-27
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L29/66
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译：公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄被提供。

7. 发明申请

US20130009211A1 SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE 审中-公开
标题翻译：硅锗膜形成方法和结构
公开(公告)号：US20130009211A1
公开(公告)日：2013-01-10
申请号：US13616994
申请日：2012-09-14
申请人： Ashima B. Chakravarti , Abhishek Dube , Dominic J. Schepis
发明人： Ashima B. Chakravarti , Abhishek Dube , Dominic J. Schepis
IPC分类号： H01L29/161 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/76224 , H01L21/823807
摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.
摘要翻译：在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。导致沉积的SiGe基本上没有生长边缘效应。

8. 发明授权

US07776624B2 Method for improving semiconductor surfaces 失效
标题翻译：改善半导体表面的方法
公开(公告)号：US07776624B2
公开(公告)日：2010-08-17
申请号：US12168945
申请日：2008-07-08
申请人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
发明人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
IPC分类号： H01L21/00
CPC分类号： H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/302 , H01L21/30604 , Y10S438/947 , Y10S438/977
摘要： A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.
摘要翻译：半导体制造方法。该方法包括提供半导体衬底，其中半导体衬底包括半导体材料。接下来，去除半导体衬底的顶部。接下来，在半导体基板上外延生长第一半导体层，其中第一半导体层中的第一半导体材料的第一原子百分比等于半导体衬底中的衬底半导体材料的衬底原子百分比。

9. 发明授权

US07759213B2 Pattern independent Si:C selective epitaxy 失效
标题翻译：图案独立Si：C选择性外延
公开(公告)号：US07759213B2
公开(公告)日：2010-07-20
申请号：US12189344
申请日：2008-08-11
申请人： Abhishek Dube , Ashima B. Chakravarti , Dominic J. Schepis
发明人： Abhishek Dube , Ashima B. Chakravarti , Dominic J. Schepis
IPC分类号： H01L21/76
CPC分类号： H01L21/02381 , H01L21/02529 , H01L21/0262 , H01L21/02639 , H01L29/66636 , H01L29/7848
摘要： Trenches are formed in a silicon substrate by etching exposed portions of the silicon substrate. After covering areas on which deposition of Si:C containing material is to be prevented, selective epitaxy is performed in a single wafer chamber at a temperature from about 550° C. to about 600° C. employing a limited carrier gas flow, i.e., at a flow rate less than 12 standard liters per minute to deposit Si:C containing regions at a pattern-independent uniform deposition rate. The inventive selective epitaxy process for Si:C deposition provides a relatively high net deposition rate a high quality Si:C crystal in which the carbon atoms are incorporated into substitutional sites as verified by X-ray diffraction.
摘要翻译：通过蚀刻硅衬底的暴露部分在硅衬底中形成沟槽。在覆盖要防止沉积含Si：C的材料的区域之后，使用有限的载气流在约550℃至约600℃的温度下，在单晶片室中进行选择性外延，即，以小于12标准升/分钟的流速，以不依赖于图案的均匀沉积速率沉积含Si：C的区域。用于Si：C沉积的本发明的选择性外延工艺提供了相对较高的净沉积速率，其中通过X射线衍射验证碳原子并入到取代位置的高质量Si：C晶体。

10. 发明申请

US20090001430A1 ELIMINATE NOTCHING IN SI POST SI-RECESS RIE TO IMPROVE EMBEDDED DOPED AND INSTRINSIC SI EPITAZIAL PROCESS 审中-公开
标题翻译：消除注意事项，以改善嵌入式印刷和印刷工艺
公开(公告)号：US20090001430A1
公开(公告)日：2009-01-01
申请号：US11771013
申请日：2007-06-29
申请人： Ashima B. Chakravarti , Renee T. Mo
发明人： Ashima B. Chakravarti , Renee T. Mo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823481 , H01L21/28176 , H01L29/66636 , H01L29/7848
摘要： A dielectric element, and method of manufacturing the same, is disclosed for a semiconductor structure which comprises a substrate having a gate formed on a top surface of the substrate. The substrate and gate define a gap in a region between the gate and the substrate. A specified amount of dielectric on the substrate, at least a portion of which is in the gap, forms the dielectric element which substantially prevents unwanted electrical connectivity between the gate and the substrate.
摘要翻译：公开了一种用于半导体结构的电介质元件及其制造方法，该半导体结构包括在衬底的顶表面上形成有栅极的衬底。衬底和栅极限定栅极和衬底之间的区域中的间隙。衬底上的至少一部分位于间隙中的指定量的电介质形成基本上防止栅极和衬底之间不必要的电连接的电介质元件。

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