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1. 发明授权

US08495553B2 Native threshold voltage switching 有权
标题翻译：本机阈值电压切换
公开(公告)号：US08495553B2
公开(公告)日：2013-07-23
申请号：US13315406
申请日：2011-12-09
申请人： George Antony , Sridhar H. Rangarajan , Alexander J. Suess
发明人： George Antony , Sridhar H. Rangarajan , Alexander J. Suess
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/78
摘要： A computer-implemented method of determining threshold voltage levels within a macro of integrated circuit cells. In one embodiment, the method includes: referencing a library of the integrated circuit cells in the macro; estimating a leakage power and a dynamic power for a first integrated circuit cell in the macro; comparing the leakage power with the dynamic power; switching the first integrated circuit cell to a low threshold voltage level in response to determining the dynamic power is greater than the leakage power; and updating the library with a voltage level of the first integrated circuit cell.
摘要翻译：一种确定集成电路单元宏块内的阈值电压电平的计算机实现的方法。在一个实施例中，该方法包括：参考宏中的集成电路单元的库; 估计宏中的第一集成电路单元的泄漏功率和动态功率; 将泄漏功率与动力功率进行比较; 响应于确定动态功率而将第一集成电路单元切换到低阈值电压电平大于泄漏功率; 以及用第一集成电路单元的电压电平更新库。

2. 发明申请

US20130152028A1 NATIVE THRESHOLD VOLTAGE SWITCHING 有权
标题翻译：电压门限开关
公开(公告)号：US20130152028A1
公开(公告)日：2013-06-13
申请号：US13315406
申请日：2011-12-09
申请人： George Antony , Sridhar H. Rangarajan , Alexander J. Suess
发明人： George Antony , Sridhar H. Rangarajan , Alexander J. Suess
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/78
摘要： A computer-implemented method of determining threshold voltage levels within a macro of integrated circuit cells. In one embodiment, the method includes: referencing a library of the integrated circuit cells in the macro; estimating a leakage power and a dynamic power for a first integrated circuit cell in the macro; comparing the leakage power with the dynamic power; switching the first integrated circuit cell to a low threshold voltage level in response to determining the dynamic power is greater than the leakage power; and updating the library with a voltage level of the first integrated circuit cell.
摘要翻译：一种确定集成电路单元宏块内的阈值电压电平的计算机实现的方法。在一个实施例中，该方法包括：参考宏中的集成电路单元的库; 估计宏中的第一集成电路单元的泄漏功率和动态功率; 将泄漏功率与动力功率进行比较; 响应于确定动态功率而将第一集成电路单元切换到低阈值电压电平大于泄漏功率; 以及用第一集成电路单元的电压电平更新库。

3. 发明申请

US20070277131A1 METHOD FOR A FAST INCREMENTAL CALCULATION OF THE IMPACT OF COUPLED NOISE ON TIMING 有权
标题翻译：快速计算耦合噪声对时序影响的方法
公开(公告)号：US20070277131A1
公开(公告)日：2007-11-29
申请号：US11420529
申请日：2006-05-26
申请人： Gregory M. Schaeffer , Alexander J. Suess , David J. Hathaway
发明人： Gregory M. Schaeffer , Alexander J. Suess , David J. Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.
摘要翻译：一种用于通过对IC执行初始定时分析来递增地计算耦合噪声对具有多个逻辑级的集成电路（IC）的定时的影响的方法，以提供耦合噪声对定时的影响的第一确定。然后执行对IC的一个或多个设计更改。响应于设计变化，耦合噪声对定时的影响是在进行改变的逻辑阶段和下游的逻辑级上计算的。然后将计算结果输入到定时分析工具，以调整进行设计更改的每个逻辑级的延迟和转换以及其下游的逻辑级。

4. 发明申请

US20120144357A1 Method for Enabling Multiple Incompatible or Costly Timing Environments for Efficient Timing Closure 有权
标题翻译：启用多个不兼容或成本高的定时环境以实现高效定时关闭的方法
公开(公告)号：US20120144357A1
公开(公告)日：2012-06-07
申请号：US12958431
申请日：2010-12-02
申请人： Frank J. Musante , William E. Dougherty , Nathaniel D. Hieter , Alexander J. Suess
发明人： Frank J. Musante , William E. Dougherty , Nathaniel D. Hieter , Alexander J. Suess
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.
摘要翻译：基于松弛值执行静态时序分析以验证和优化逻辑设计的方法包括：在所述逻辑设计内选择具有至少两个输入的已知值的一个或多个电路; 识别从所述已知值的输入中控制所选择的电路的输出到达时间的关键输入; 基于关键和非关键输入的到达时间之间的差异，确定电路的一个或多个非关键输入的所需到达时间; 并且基于关键和非关键输入的AT之间的差异来计算关键输入上的松弛。基于由到达时间差定义的松弛的设计优化优选地使用反向合并边缘设计度量。该度量确定时钟整形电路的非关键信号的输入到达时间的确切需要量的改善。

5. 发明授权

US08302049B2 Method for enabling multiple incompatible or costly timing environment for efficient timing closure 有权
标题翻译：用于实现多个不兼容或昂贵的定时环境以实现有效的定时关闭的方法
公开(公告)号：US08302049B2
公开(公告)日：2012-10-30
申请号：US12958431
申请日：2010-12-02
申请人： Frank J. Musante , William E. Dougherty , Nathaniel D. Hieter , Alexander J. Suess
发明人： Frank J. Musante , William E. Dougherty , Nathaniel D. Hieter , Alexander J. Suess
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.
摘要翻译：基于松弛值执行静态时序分析以验证和优化逻辑设计的方法包括：在所述逻辑设计内选择具有至少两个输入的已知值的一个或多个电路; 识别从所述已知值的输入中控制所选择的电路的输出到达时间的关键输入; 基于关键和非关键输入的到达时间之间的差异，确定电路的一个或多个非关键输入所需的到达时间; 并且基于关键和非关键输入的AT之间的差异来计算关键输入上的松弛。基于由到达时间差定义的松弛的设计优化优选地使用反向合并边缘设计度量。该度量确定时钟整形电路的非关键信号的输入到达时间的确切需要量的改善。

6. 发明授权

US07650246B2 Process and apparatus for estimating circuit delay 失效
标题翻译：用于估计电路延迟的过程和装置
公开(公告)号：US07650246B2
公开(公告)日：2010-01-19
申请号：US11162200
申请日：2005-08-31
申请人： Harry J. Beatty, III , David J. Hathaway , Alexander J. Suess
发明人： Harry J. Beatty, III , David J. Hathaway , Alexander J. Suess
IPC分类号： G01R15/00 , G06F19/00
CPC分类号： G01R31/31725
摘要： A method and device for determining a delay of a gate driven by a driving gate with different ground or supply voltages. The method includes determining from the supply and ground voltages for the driven gate and its driving gate an adjusted supply voltage value, and applying the adjusted supply voltage value as a single voltage parameter to a pre-characterized delay model for the driven gate. The device is structured to perform the method.
摘要翻译：一种用于确定由具有不同接地或电源电压的驱动门驱动的栅极的延迟的方法和装置。该方法包括从驱动栅极及其驱动栅极的电源和地电压确定经调整的电源电压值，并将调整的电源电压值作为单个电压参数应用于驱动栅极的预定义延迟模型。该设备的结构是执行该方法。

7. 发明申请

US20080263488A1 METHOD FOR GENERATING A SKEW SCHEDULE FOR A CLOCK DISTRIBUTION NETWORK CONTAINING GATING ELEMENTS 有权
标题翻译：用于生成包含加注元素的时钟分配网络的SKEW时间表的方法
公开(公告)号：US20080263488A1
公开(公告)日：2008-10-23
申请号：US11737289
申请日：2007-04-19
申请人： Revanta Banerji , David J. Hathaway , Alex Rubin , Alexander J. Suess
发明人： Revanta Banerji , David J. Hathaway , Alex Rubin , Alexander J. Suess
IPC分类号： G06F17/50 , H03H11/26
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.
摘要翻译：用于产生时钟分配网络的偏斜调度的方法产生考虑时钟分配网络的端点处的存储器元件的定时要求以及提供时钟门和其它时钟控制的门控信号的定时要求的调度时钟分配网络中的元素。该方法通过两阶段迭代过程为偏斜调度问题提供了一个完整的解决方案。该过程的两个阶段交替地跟踪通过首先考虑时钟分配网络的门控元件产生的调度，然后平衡可能存在于相同时钟分配网络的存储器元件上的任何剩余的偏移。最后，该方法描述了用于后处理偏斜调度以确保可以使用时钟树生成工具来实现的过程。

8. 发明授权

US07117466B2 System and method for correlated process pessimism removal for static timing analysis 失效
标题翻译：静态时序分析相关过程悲观消除的系统和方法
公开(公告)号：US07117466B2
公开(公告)日：2006-10-03
申请号：US10665273
申请日：2003-09-18
申请人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
发明人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.
摘要翻译：描述了静态时序分析中消除悲观情绪的方法。延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。分析以路径为基础进行。通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。

9. 发明授权

US06615395B1 Method for handling coupling effects in static timing analysis 失效
标题翻译：在静态时序分析中处理耦合效应的方法
公开(公告)号：US06615395B1
公开(公告)日：2003-09-02
申请号：US09467208
申请日：1999-12-20
申请人： David J. Hathaway , Chandramouli V. Kashyap , Byron L. Krauter , Sharad Mehrotra , Alexander J. Suess
发明人： David J. Hathaway , Chandramouli V. Kashyap , Byron L. Krauter , Sharad Mehrotra , Alexander J. Suess
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method for performing a static timing analysis on an integrated circuit chip or module taking into account the effect of wiring interconnection coupling is described. The wiring interactions are modeled as appropriate equivalent grounded capacitances, allowing traditional delay calculation methods to be applied. The method includes the steps of assigning a pessimistic value to the wiring coupling interaction between nets forming the integrated circuit chip; performing the static timing analysis using computed timing parameters which are a function of net capacitance, the net capacitance being based on the pessimistic value of the coupling interaction between the nets; updating the net capacitance of selected nets based on 1) an overlap between an arrival time window of each of the selected nets and a possible arrival time window of each of the other nets which are coupled to the each of selected nets, and 2) on the slew of each of the selected nets and the slew of each of the other nets which are coupled to the selected nets; and updating the static timing analysis based on the updated net capacitances of the selected nets.
摘要翻译：描述了考虑到布线互连耦合的影响，在集成电路芯片或模块上执行静态时序分析的方法。布线相互作用被建模为适当的等效接地电容，允许应用传统的延迟计算方法。该方法包括以下步骤：为形成集成电路芯片的网络之间的布线耦合交互分配悲观值; 使用作为净电容的函数的计算定时参数来执行静态时序分析，净电容基于网络之间的耦合相互作用的悲观值; 基于以下步骤更新所选网络的净电容：1）每个所选网络的到达时间窗口与耦合到所选网络中的每一个网络的每个其它网络的可能到达时间窗口之间的重叠，以及2）所选择的网络中的每一个的转换以及耦合到所选择的网络的每个其他网络的转换; 以及基于所选网络的更新的净电容来更新静态时序分析。

10. 发明授权

US07937604B2 Method for generating a skew schedule for a clock distribution network containing gating elements 有权
标题翻译：用于产生包含门控元件的时钟分配网络的偏斜调度的方法
公开(公告)号：US07937604B2
公开(公告)日：2011-05-03
申请号：US11737289
申请日：2007-04-19
申请人： Revanta Banerji , David J. Hathaway , Alex Rubin , Alexander J. Suess
发明人： Revanta Banerji , David J. Hathaway , Alex Rubin , Alexander J. Suess
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.
摘要翻译：用于产生时钟分配网络的偏斜调度的方法产生考虑时钟分配网络的端点处的存储器元件的定时要求以及提供时钟门和其它时钟控制的门控信号的定时要求的调度时钟分配网络中的元素。该方法通过两阶段迭代过程为偏斜调度问题提供了一个完整的解决方案。该过程的两个阶段交替地跟踪通过首先考虑时钟分配网络的门控元件产生的调度，然后平衡可能存在于相同时钟分配网络的存储器元件上的任何剩余的偏移。最后，该方法描述了用于后处理偏斜调度以确保可以使用时钟树生成工具来实现的过程。

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