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1. 发明授权

US06480044B2 Semiconductor circuit configuration 失效
标题翻译：半导体电路配置
公开(公告)号：US06480044B2
公开(公告)日：2002-11-12
申请号：US09804322
申请日：2001-03-12
申请人： Georg Braun , Heinz Hönigschmid , Kurt Hoffmann , Oskar Kowarik
发明人： Georg Braun , Heinz Hönigschmid , Kurt Hoffmann , Oskar Kowarik
IPC分类号： H03K300
CPC分类号： G11C16/08 , G11C8/10
摘要： A semiconductor circuit is disclosed which contains a driving circuit which is integrated into a semiconductor substrate of a first conductivity type and includes positive voltage switching transistors for switching positive and/or zero voltage levels and negative switching transistors for switching negative and/or zero voltage levels. In addition, the driving circuit contains a control circuit which is positioned upstream from the driving circuit and is also embodied in the semiconductor substrate, which is connected to a substrate voltage. A negative voltage switching transistor of the driving circuit is configured inside an outer well which is embedded in the semiconductor substrate and is of a second conductivity type which is opposite to the first, and the outer well is connected to a supply voltage.
摘要翻译：公开了一种半导体电路，其包含集成到第一导电类型的半导体衬底中的驱动电路，并且包括用于切换正和/或零电压电平的正电压开关晶体管和用于切换负和/或零电压电平的负开关晶体管。此外，驱动电路包括位于驱动电路上游的控制电路，并且还被配置在连接到衬底电压的半导体衬底中。驱动电路的负电压开关晶体管被配置在嵌入在半导体衬底中的外部阱中，并且是与第一导电类型相反的第二导电类型，并且外部阱连接到电源电压。

2. 发明授权

US06392918B2 Circuit configuration for generating a reference voltage for reading a ferroelectric memory 有权
标题翻译：用于产生用于读取铁电存储器的参考电压的电路配置
公开(公告)号：US06392918B2
公开(公告)日：2002-05-21
申请号：US09817578
申请日：2001-03-26
申请人： Georg Braun , Heinz Hönigschmid , Kurt Hoffmann , Oskar Kowarik , Thomas Röhr
发明人： Georg Braun , Heinz Hönigschmid , Kurt Hoffmann , Oskar Kowarik , Thomas Röhr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.
摘要翻译：用于产生用于读出的参考电压的电路和用于经由位线从铁电存储器的存储单元以恒定板电压读出的读取输出信号的评估。在该电路中，参考电压装置由经受互补信号的作用的两个参考单元形成。可以同时读出参考单元，以便在选择和评估装置中产生参考电压。

3. 发明授权

US06538950B2 Integrated memory and corresponding operating method 有权
公开(公告)号：US06538950B2
公开(公告)日：2003-03-25
申请号：US09917553
申请日：2001-07-27
申请人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
发明人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
IPC分类号： G11C800
CPC分类号： G11C7/06 , G11C7/065 , G11C7/1006
摘要： An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

4. 发明授权

US06480055B2 Decoder element for generating an output signal having three different potentials and an operating method for the decoder element 有权
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件和用于解码器元件的操作方法
公开(公告)号：US06480055B2
公开(公告)日：2002-11-12
申请号：US09822028
申请日：2001-03-29
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
IPC分类号： H03K1776
CPC分类号： G11C5/143 , G11C8/08 , G11C16/12 , H03K19/09425 , H03M5/16
摘要： A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.
摘要翻译：解码器元件设置有输出，由此产生具有三种不同可能电位之一的输出信号。输出信号可以具有第一电位，第二电位和第三电位的值，其中第二电位位于第一电位和第三电位之间。输出信号根据解码器元件的端子连接处的输入信号的电压值而产生。

5. 发明授权

US06434039B1 Circuit configuration for reading a memory cell having a ferroelectric capacitor 有权
标题翻译：用于读取具有铁电电容器的存储单元的电路配置
公开(公告)号：US06434039B1
公开(公告)日：2002-08-13
申请号：US09838750
申请日：2001-04-19
申请人： Georg Braun , Heinz Hönigschmid
发明人： Georg Braun , Heinz Hönigschmid
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A circuit configuration for reading a ferroelectric memory cell which has a ferroelectric capacitor is described. The memory cell is connected to a bit line. The circuit configuration provides a differential amplifier having a first differential amplifier input, a second differential amplifier input and a differential amplifier output. The first differential amplifier input is connected to the bit line, and the second differential amplifier input is connected to a reference signal. A first driver input of a first driver circuit is connected to the differential amplifier output, and a first driver output is connected to the bit line. The differential amplifier is fed back through the first driver circuit and regulates the bit line voltage to the voltage value of the reference signal.
摘要翻译：描述用于读取具有铁电电容器的铁电存储单元的电路结构。存储单元连接到位线。电路配置提供了具有第一差分放大器输入，第二差分放大器输入和差分放大器输出的差分放大器。第一差分放大器输入连接到位线，第二差分放大器输入连接到参考信号。第一驱动电路的第一驱动器输入端连接到差分放大器输出，第一驱动器输出端连接到位线。差分放大器通过第一驱动电路反馈，并将位线电压调节到参考信号的电压值。

6. 发明授权

US06396750B2 Integrated memory with redundancy and method for repairing an integrated memory 失效
公开(公告)号：US06396750B2
公开(公告)日：2002-05-28
申请号：US09888022
申请日：2001-06-22
申请人： Heinz Hönigschmid , Georg Braun , Andrej Majdic
发明人： Heinz Hönigschmid , Georg Braun , Andrej Majdic
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C29/702
摘要： An integrated memory has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and connected to a data line and amplifies data read from the normal memory cells. Furthermore, the memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected on the one hand to the line and on the other hand to the data line and, in the redundancy situation, serves for amplifying the data read from the normal memory cells. A method for repairing an integrated memory is also provided.

7. 发明授权

US06525974B2 Integrated memory with redundancy 有权
公开(公告)号：US06525974B2
公开(公告)日：2003-02-25
申请号：US09888023
申请日：2001-06-22
申请人： Ernst Neuhold , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Böhm , Thomas Röhr
发明人： Ernst Neuhold , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Böhm , Thomas Röhr
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/846
摘要： An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

8. 发明授权

US06459626B1 Integrated memory having memory cells and reference cells, and corresponding operating method 有权
公开(公告)号：US06459626B1
公开(公告)日：2002-10-01
申请号：US09962703
申请日：2001-09-24
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
IPC分类号： G11C700
CPC分类号： G11C7/14 , G11C11/22
摘要： An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

9. 发明授权

US06442100B2 Integrated memory 有权
标题翻译：集成内存
公开(公告)号：US06442100B2
公开(公告)日：2002-08-27
申请号：US09904358
申请日：2001-07-12
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
IPC分类号： G11C800
CPC分类号： G11C7/06 , G11C7/1048 , G11C11/22
摘要： The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.
摘要翻译：集成存储器具有通过开关元件连接到读写放大器的输入的m≥1位线。每个读或写访问只有一个开关元件被导电连接。存储器设置有影响通过读写放大器和位线发生的读取或写入访问的切换单元。电路单元具有激活输入。列端解码器具有第一解码器级和m个第二解码器级。第二解码器级的输出端连接到每个开关元件的控制输入端。第一解码器级的输出连接到开关单元的启动输入。

10. 发明授权

US06487128B2 Integrated memory having memory cells and reference cells, and operating method for such a memory 有权
标题翻译：具有存储单元和参考单元的集成存储器以及用于这种存储器的操作方法
公开(公告)号：US06487128B2
公开(公告)日：2002-11-26
申请号：US09962411
申请日：2001-09-24
申请人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
发明人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/14
摘要： The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.
摘要翻译：存储器具有相同构造的存储器单元和参考单元。通过经由第一开关元件将读取放大器的参考单元解耦，并且经由第二开关元件将连接到参考单元的位线的一部分电连接到电位线，将参考信息项写入参考单元携带参考信息。

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