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1. 发明申请

US20060227627A1 Buffer component for a memory module, and a memory module and a memory system having such buffer component 有权
标题翻译：用于存储器模块的缓冲器组件，以及具有这种缓冲器组件的存储器模块和存储器系统
公开(公告)号：US20060227627A1
公开(公告)日：2006-10-12
申请号：US11368267
申请日：2006-03-03
申请人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
发明人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
IPC分类号： G11C7/10
CPC分类号： G11C5/063 , G06F13/1689 , G11C5/04 , G11C7/1078 , G11C7/109
摘要： The invention relates to a buffer component for a memory module having a plurality of memory components, comprising a first data interface for receiving an item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signals, and a control unit which applies the address and command signals to the plurality of memory components during a first clock period of the clock signal and applies the control signal for activating the group of the plurality of memory components to the group of the plurality of memory components to be activated when address and command signals are present, in a succeeding second clock period of the clock signal, whereby the address and command signals present are accepted into the group of the plurality of memory components.
摘要翻译：本发明涉及一种用于具有多个存储器组件的存储器模块的缓冲器组件，包括：第一数据接口，用于根据数据传输协议接收访问信息项，地址，时钟，控制和命令信号取决于访问信息，用于驱动时钟信号的第二数据接口，以及对多个存储器组件的地址和命令信号，以及根据信令协议将控制信号驱动到多组存储器组件的一组，其中激活存储器组件和地址和命令信号的接受以取决于控制信号的方式实现;以及控制单元，其在时钟信号的第一时钟周期期间将地址和命令信号施加到多个存储器组件并应用所述控制信号用于将所述多个存储器组件的组激活到所述多个组中的组在时钟信号的随后的第二时钟周期中存在地址和命令信号时被激活的多路分量，由此存在的地址和命令信号被接收到多个存储器组件的组中。

2. 发明授权

US07646650B2 Buffer component for a memory module, and a memory module and a memory system having such buffer component 有权
标题翻译：用于存储器模块的缓冲器组件，以及具有这种缓冲器组件的存储器模块和存储器系统
公开(公告)号：US07646650B2
公开(公告)日：2010-01-12
申请号：US11368267
申请日：2006-03-03
申请人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
发明人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
IPC分类号： G11C7/10
CPC分类号： G11C5/063 , G06F13/1689 , G11C5/04 , G11C7/1078 , G11C7/109
摘要： A buffer component for a memory module having a plurality of memory components includes item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signals, and a control unit which applies the address and command signals to the plurality of memory components during a first clock period of the clock signal and applies the control signal for activating the group of the plurality of memory components to the group of the plurality of memory components to be activated when address and command signals are present, in a succeeding second clock period of the clock signal, whereby the address and command signals present are accepted into the group of the plurality of memory components.
摘要翻译：具有多个存储器组件的存储器模块的缓冲器组件包括根据数据传输协议的访问信息项，取决于访问信息的地址，时钟，控制和命令信号，用于驱动时钟信号的第二数据接口以及根据信令协议对多个存储器组件的地址和命令信号以及用于将控制信号驱动到一组多个存储器组件，其中存储器组件的激活和地址和命令信号的接受是以取决于控制信号的方式实现;以及控制单元，其在时钟信号的第一时钟周期期间将地址和命令信号施加到多个存储器组件，并施加用于激活多个存储器的组的控制信号当地址和命令信号时，要激活的多个存储器组件的组件的组件存在于时钟信号的随后的第二时钟周期中，由此存在的地址和命令信号被接收到多个存储器组件的组中。

3. 发明授权

US07149864B2 Method and circuit for allocating memory arrangement addresses 有权
标题翻译：分配存储器配置地址的方法和电路
公开(公告)号：US07149864B2
公开(公告)日：2006-12-12
申请号：US10777992
申请日：2004-02-12
申请人： Georg Braun , Andreas Jakobs
发明人： Georg Braun , Andreas Jakobs
IPC分类号： G06F12/02
CPC分类号： G06F12/0669
摘要： Methods and apparatus for allocating memory arrangement addresses to a buffer chip, during an initialization mode, for use in addressing one or more memory arrangements connected to the buffer chip are provided. A buffer circuit may receive first initialization data specifying a first set of available memory arrangement addresses and associate one or more of the first set of available memory arrangement addresses with the one or more memory arrangements connected to the buffer chip. The buffer circuit may also generate second initialization data specifying the set of available memory arrangement addresses available after the association. The second initialization data may be transmitted to another buffer circuit for use in address allocation or back to a memory access control unit.
摘要翻译：提供了用于在初始化模式期间将存储器布置地址分配给缓冲器芯片用于寻址连接到缓冲器芯片的一个或多个存储器配置的方法和装置。缓冲器电路可以接收指定第一组可用存储器布置地址的第一初始化数据，并将第一组可用存储器配置地址中的一个或多个与连接到缓冲器芯片的一个或多个存储器配置相关联。缓冲电路还可以产生指定在关联之后可用的可用存储器布置地址的集合的第二初始化数据。第二初始化数据可以被发送到用于地址分配的另一缓冲电路或者返回到存储器访问控制单元。

4. 发明申请

US20060262613A1 Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted 有权
标题翻译：半导体存储器和方法，用于在接收要发送的写入数据期间适配时钟信号和选通信号之间的相位关系
公开(公告)号：US20060262613A1
公开(公告)日：2006-11-23
申请号：US11410320
申请日：2006-04-24
申请人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
发明人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.
摘要翻译：提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

5. 发明授权

US07457174B2 Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted 有权
标题翻译：半导体存储器和方法，用于在接收要发送的写入数据期间适配时钟信号和选通信号之间的相位关系
公开(公告)号：US07457174B2
公开(公告)日：2008-11-25
申请号：US11410320
申请日：2006-04-24
申请人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
发明人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.
摘要翻译：提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

6. 发明申请

US20060197566A1 DLL circuit for providing an output signal with a desired phase shift 审中-公开
标题翻译： DLL电路，用于提供具有所需相移的输出信号
公开(公告)号：US20060197566A1
公开(公告)日：2006-09-07
申请号：US11358940
申请日：2006-02-21
申请人： Andreas Jakobs , Andreas Taeuber
发明人： Andreas Jakobs , Andreas Taeuber
IPC分类号： H03L7/06
CPC分类号： H03K5/131
摘要： The present invention relates to a DLL circuit for providing an output signal which is shifted with by a desired phase shift with respect to a periodic input signal. In one embodiment, the DLL Circuit comprises a plurality of delay elements all having the same delay time and being connected in series to form a delay chain, wherein the periodic input signal is applied to the first delay element of the delay chain. The DLL circuit further comprises a detection unit which is connected to the outputs of at least a portion of the delay elements and which is provided to determine which delay element a particular edge of the periodic signal has reached after a predetermined phase progress of the periodic signal, and to generate a corresponding control information which indicates at which delay element the particular edge of the periodic signal has last been determined. The DLL circuit further comprises a selection circuit for selecting one of the delay elements depending on the control information and depending on the desired phase shift and outputting the signal at the output of the selected delay elements as the output signal of the DLL circuit.
摘要翻译：本发明涉及一种用于提供输出信号的DLL电路，该输出信号相对于周期性输入信号被移位期望的相移。在一个实施例中，DLL电路包括多个具有相同延迟时间并被串联连接以形成延迟链的延迟元件，其中周期性输入信号被施加到延迟链的第一延迟元件。 DLL电路还包括检测单元，其连接到延迟元件的至少一部分的输出，并且被提供用于确定在周期信号的预定相位进行之后周期信号的特定边缘已经到达的延迟元件并且产生相应的控制信息，该控制信息指示周期信号的特定边缘最后被确定在哪个延迟元件。 DLL电路还包括一个选择电路，用于根据控制信息选择一个延迟元件，并根据期望的相移，并输出所选延迟元件的输出端的信号作为DLL电路的输出信号。

7. 发明申请

US20060049967A1 Code driver for a memory controller 审中-公开
标题翻译：内存控制器的代码驱动程序
公开(公告)号：US20060049967A1
公开(公告)日：2006-03-09
申请号：US11213550
申请日：2005-08-26
申请人： Andreas Jakobs , Peter Gregorius
发明人： Andreas Jakobs , Peter Gregorius
IPC分类号： H03M7/00
CPC分类号： H04J13/16
摘要： A code driver is described having a codeword source, which has n>1 source terminals and is designed to output at these terminals a sequence of n-digit codewords, each in the form of n parallel code characters, and having n parallel transmission paths between the n source terminals and n transmit terminals for sending the message represented by the codewords to a receiver. According to the invention, a selection device is provided, which indicates explicitly for each codeword which of the n digits of the codeword concerned are relevant to the decoding of the message in the receiver, and which, dependent on this explicit indication, activates only those of the n transmission paths that are assigned to the relevant digits of the codeword.
摘要翻译：描述了具有代码字源的代码驱动器，其具有n≥1个源极端子，并且被设计为在这些端子处输出n个数字码字序列，每个n个码字码字以n个并行码字符的形式，并且具有n个并行传输路径， n个源终端和n个发送终端，用于将由码字表示的消息发送到接收机。根据本发明，提供了一种选择装置，其针对每个码字明确地指示所涉及的码字的n位的哪一个与接收机中的消息的解码相关，并且根据该显式指示仅激活那些分配给码字的相关数字的n个传输路径。

8. 发明申请

US20050044305A1 Semiconductor memory module 失效
标题翻译：半导体存储器模块
公开(公告)号：US20050044305A1
公开(公告)日：2005-02-24
申请号：US10887019
申请日：2004-07-08
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G06F12/00 , G06F13/16 , G11C5/06 , G11C7/10 , G11C11/41
CPC分类号： G11C5/063
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.
摘要翻译：本发明涉及一种半导体存储器模块，其具有布置在至少一行的多个存储器芯片和至少一个缓冲器芯片，该缓冲器芯片驱动并接收时钟信号，以及将命令和寻址信号存储到存储器芯片以及从存储器芯片传送数据信号通过模块内的时钟，地址，命令和数据总线，并形成与外部主存储器总线的接口。半导体存储器模块具有布置在其上的偶数个缓冲器芯片，并且所有存储器芯片至少通过一个信号线类型从信号组连接到两个相应的缓冲器芯片，并且仅剩下两个缓冲器芯片之一来自该组的信号线。在读取操作期间，通过其线从一个缓冲芯片到相应的一个存储器芯片的致动信号的电信号传播时间和从该存储器芯片到另一个缓冲器芯片的数据信号的电信号传播时间之和对于所有存储器芯片是相同的，并且提供用于控制到存储器芯片或从存储器芯片的相应数据写入和读取操作的控制装置，以便以与数据相同的相同方向驱动时钟信号和命令和寻址信号当数据被写入和读取时通过模块内的总线发送信号。

9. 发明申请

US20090206896A1 DELAY LOCKED LOOP 失效
标题翻译：延迟锁定环
公开(公告)号：US20090206896A1
公开(公告)日：2009-08-20
申请号：US12031429
申请日：2008-02-14
申请人： Andreas Jakobs
发明人： Andreas Jakobs
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/087 , H03L7/10
摘要： An integrated circuit includes a chain of delay elements, a first phase detector, and a controller. The chain of delay elements is configured to delay an input clock signal for providing an output clock signal phase shifted with respect to the input clock signal by a selected value. The first phase detector is configured to provide a common control signal to each delay element based on a phase difference between the input clock signal and a signal output from one of the delay elements to adjust a delay of each delay element. The controller is configured to provide an independent control signal to each delay element to individually adjust the delay of each delay element such that the delay of each delay element is equal.
摘要翻译：集成电路包括延迟元件链，第一相位检测器和控制器。延迟元件链被配置为延迟输入时钟信号，以提供相对于输入时钟信号相移的输出时钟信号所选择的值。第一相位检测器被配置为基于输入时钟信号和从延迟元件之一输出的信号之间的相位差来向每个延迟元件提供公共控制信号，以调整每个延迟元件的延迟。控制器被配置为向每个延迟元件提供独立的控制信号以分别调整每个延迟元件的延迟，使得每个延迟元件的延迟相等。

10. 发明申请

US20090195258A1 CONTROLLING AN ANALOG SIGNAL IN AN INTEGRATED CIRCUIT 有权
标题翻译：控制集成电路中的模拟信号
公开(公告)号：US20090195258A1
公开(公告)日：2009-08-06
申请号：US12026143
申请日：2008-02-05
申请人： Andreas Jakobs
发明人： Andreas Jakobs
IPC分类号： G01R35/00
CPC分类号： G11C5/063 , G11C7/1066 , G11C2207/2254
摘要： A method of controlling an analog signal in an integrated circuit includes generating a first control signal having a first predetermined duration within the integrated circuit. The first control signal is configured to cause the analog signal to have a first signal level. The first signal level is compared to a level of a target signal. A second control signal is generated within the integrated circuit based on a result of the comparison. The second control signal is configured to cause the analog signal to have a second signal level. The second control signal has a second predetermined duration that is different than the first predetermined duration.
摘要翻译：一种在集成电路中控制模拟信号的方法包括：在集成电路内产生具有第一预定持续时间的第一控制信号。第一控制信号被配置为使得模拟信号具有第一信号电平。将第一信号电平与目标信号的电平进行比较。基于比较的结果，在集成电路内产生第二控制信号。第二控制信号被配置为使得模拟信号具有第二信号电平。第二控制信号具有与第一预定持续时间不同的第二预定持续时间。

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