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    • 6. 发明授权
    • Method and apparatus for multiplex control of a plurality of stepper
motors
    • 多个步进马达的多路复用控制方法和装置
    • US5583410A
    • 1996-12-10
    • US326980
    • 1994-10-21
    • Gary S. JacobsonWesley A. KirschnerMichael J. Ramadei
    • Gary S. JacobsonWesley A. KirschnerMichael J. Ramadei
    • G05B19/40
    • G05B19/40G05B2219/34045G05B2219/34196G05B2219/34219G05B2219/34236G05B2219/35366G05B2219/35368G05B2219/35375G05B2219/42171G05B2219/42198
    • A plurality of step time tables consisting of a sequence of step times defining intervals between steps and thus a velocity profile to be executed by a stepper motor are stored in a first memory. A step table defining a plurality of identical sequences of excitation pattern for driving a stepper motor is stored in a second table. Identical DMA channels output the step times to a timer and the plurality of exitation patterns to a buffer. The timer measures the duration of the step times and when each step time expires generates a trigger signal which initiates the transfer of the next step time and next excitation pattern through the respective DMA channels. The buffer includes a control register which selects one excitation pattern from the plurality of excitation patterns output from the step table to be output for control of a selected one of a plurality of motors connected to the buffer. The buffer outputs are inverted to form bipolar signals to drive current drivers in accordance with the excitation pattern. The apparatus is initialized by a data processor to select one of the plurality of excitation tables and to select one of the groups of outputs of the buffer to drive a corresponding selected motor. The DMA channel for outputting the step time table is initialized for non-repetitive operation and the DMA channel outputting the step table is initialized for cyclic operation. The direction in which the selected stepper motor is to be driven is determined by the direction in which the step table is accessed.
    • 由步进时间序列组成的多个步进时间表被存储在第一存储器中,所述步骤时间序列确定步骤之间的间隔,从而由步进电动机执行的速度分布。 定义用于驱动步进电机的多个相同的激励模式序列的步骤表被存储在第二表中。 相同的DMA通道将步进时间输出到定时器,并将多个退出模式输出到缓冲器。 定时器测量步进时间的持续时间,并且当每个步骤时间到期时,产生触发信号,该触发信号通过相应的DMA通道启动下一个步进时间和下一个激励模式的传送。 该缓冲器包括一个控制寄存器,该控制寄存器从输出步进表的多个激励模式中选择一个激励模式,以输出以控制连接到缓冲器的多个电动机中选定的一个。 缓冲器输出被反相以形成双极信号,以根据激励模式驱动电流驱动器。 所述装置由数据处理器初始化以选择所述多个激励表中的一个,并且选择所述缓冲器的输出组之一以驱动对应的所选择的电动机。 用于输出步进时间表的DMA通道被初始化用于非重复操作,并且输出步骤表的DMA通道被初始化用于循环操作。 所选择的步进电动机的驱动方向由步进台的访问方向决定。
    • 9. 发明授权
    • System and method for efficient uncorrectable error detection in flash memory
    • 闪存中有效的不可校正错误检测的系统和方法
    • US07707481B2
    • 2010-04-27
    • US11436171
    • 2006-05-16
    • Wesley A. KirschnerRobert W. SissonJohn A. HurdGary S. Jacobson
    • Wesley A. KirschnerRobert W. SissonJohn A. HurdGary S. Jacobson
    • G11C29/00
    • G06F11/1012
    • A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data is first processed by a hash function and hash data is stored with the user data. Then, the user data and hash data are processed by the ECC system. In detection, the hash ensures that a relatively low bit-strength ECC system did not incorrectly manipulate the user data. Such a hash integrity check provides an efficient, robust detection of incorrectly corrected user data resulting from errors beyond the correction but strength of the ECC system utilized.
    • 描述了一种用于闪存中有效的不可校正错误检测的系统和方法。 包括非易失性闪速存储器的微控制器利用具有一定的错误检测和校正位强度的纠错码(ECC)。 用户数据首先通过散列函数处理,散列数据与用户数据一起存储。 然后,ECC系统处理用户数据和散列数据。 在检测中,散列确保相对较低的位强ECC系统不会错误地操纵用户数据。 这样的散列完整性检查提供了对错误校正的用户数据的有效的,鲁棒的检测,该错误纠正的用户数据是由于校正之外的错误而导致的ECC系统的强度。