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1. 发明授权

US5517665A System for controlling arbitration using the memory request signal types generated by the plurality of datapaths having dual-ported local memory architecture for simultaneous data transmission 失效
标题翻译：用于使用由具有双端口本地存储器架构的多个数据路径生成的存储器请求信号类型来控制仲裁的系统，用于同时数据传输
公开(公告)号：US5517665A
公开(公告)日：1996-05-14
申请号：US230915
申请日：1994-04-21
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F9/30 , G06F9/38 , G06F15/16 , G06F13/00
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863 , G06F9/3887
摘要： A system and method for processing data. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to gram to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.
摘要翻译：一种用于处理数据的系统和方法。根据优选实施例，系统包括全局存储器和多个数据路径。每个数据路径包括用于执行指令序列的指令并根据指令提供多个存储器请求信号类型的数据路径处理器，本地存储器，用于在本地存储器和全局存储器之间传送数据的全局端口，以及双重端口包括用于在本地存储器和数据路径处理器之间传送数据的第一和第二本地端口，其中第一和第二本地端口允许在本地存储器和数据路径处理器之间同时传输数据。该系统包括耦合到全局存储器的数据总线，用于将数据传送到全局存储器和从全局存储器传送数据;以及传输控制器，用于通过数据总线控制本地存储器和全局存储器之间的块传输和标量数据传输，并且用于在竞争中进行仲裁根据由多个数据路径的数据路径生成的存储器请求信号的信号类型，将多个数据路径的数据路径克化为对数据总线的选择的数据路径访问。

2. 发明授权

US5548793A System for controlling arbitration using the memory request signal types generated by the plurality of datapaths 失效
标题翻译：用于使用由多个数据路径生成的存储器请求信号类型来控制仲裁的系统
公开(公告)号：US5548793A
公开(公告)日：1996-08-20
申请号：US230899
申请日：1994-04-21
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F9/30 , G06F9/38 , G06F13/00 , G06F15/16
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863 , G06F9/3887
摘要： A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to grant to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.
摘要翻译：一种用于在存储器请求之间进行仲裁的系统和方法。根据优选实施例，系统包括全局存储器和多个数据路径。每个数据路径包括用于执行指令序列的指令并根据指令提供多个存储器请求信号类型的数据路径处理器，其中多个存储器请求信号类型包括指令存储器请求信号，标量存储器请求信号，输入和先出存储器请求信号，统计解码器存储器请求信号和块传送存储器请求信号。每个数据路径还包括本地存储器，用于在本地存储器和全局存储器之间传送数据的全局端口，以及包括用于在本地存储器和数据路口处理器之间传送数据的第一和第二本地端口的双端口，其中第一和第二本地端口允许在本地存储器和数据路径处理器之间同时传输数据。该系统包括耦合到全局存储器的数据总线，用于将数据传送到全局存储器和从全局存储器传送数据;以及传输控制器，用于通过数据总线控制本地存储器和全局存储器之间的块传输和标量数据传输，并且用于在竞争中进行仲裁根据由多个数据路径的数据路径生成的存储器请求信号的信号类型，多个数据路径的数据路径被授权给对数据总线的选择的数据路径访问。

3. 发明授权

US5530884A System with plurality of datapaths having dual-ported local memory architecture for converting prefetched variable length data to fixed length decoded data 失效
标题翻译：具有多个具有双端口本地存储器架构的数据路径的系统，用于将预取的可变长度数据转换为固定长度解码数据
公开(公告)号：US5530884A
公开(公告)日：1996-06-25
申请号：US230900
申请日：1994-04-21
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F9/30 , G06F9/38 , G06F3/00 , G06F15/16
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863 , G06F9/3887
摘要： A method and apparatus for processing data. According to a preferred embodiment, the apparatus comprises a plurality of datapaths, each datapath comprising datapath processor, and a statistical decoder input channel device. The statistical decoder input channel device prefetches variable length encoded data from a variable length encoded data source in response to a request by a program running on a datapath processor of a datapath of the plurality of datapaths. The statistical decoder input channel device comprises a statistical decoder processor and memory for decoding the variable length encoded data to provide fixed length decoded data, and a transmission output channel for transmitting the fixed length decoded data to the datapath.
摘要翻译：一种处理数据的方法和装置。根据优选实施例，该装置包括多个数据路径，每个数据路径包括数据路径处理器和统计解码器输入通道设备。响应于在多个数据路径的数据通路的数据路径处理器上运行的程序的请求，统计解码器输入通道设备从可变长度编码数据源预取可变长度编码数据。统计解码器输入通道装置包括统计解码器处理器和用于解码可变长度编码数据以提供固定长度解码数据的存储器，以及用于将固定长度解码数据发送到数据路径的发送输出通道。

4. 发明授权

US06812046B2 Method and apparatus for electronically aligning capacitively coupled chip pads 有权
标题翻译：用于电子对准电容耦合芯片焊盘的方法和装置
公开(公告)号：US06812046B2
公开(公告)日：2004-11-02
申请号：US10207671
申请日：2002-07-29
申请人： Robert J. Drost , Ivan E. Sutherland , Gregory M. Papadopoulos
发明人： Robert J. Drost , Ivan E. Sutherland , Gregory M. Papadopoulos
IPC分类号： H01L2166
CPC分类号： H04B5/0012 , G06F17/5077 , H01L23/48 , H01L23/544 , H01L2223/54473 , H01L2225/06531 , H01L2924/0002 , H01L2924/0001
摘要： One embodiment of the present invention provides a system that electronically aligns pads on different semiconductor chips to facilitate communication between the semiconductor chips through capacitive coupling. The system operates by measuring an alignment between a first chip and a second chip, wherein the first chip is situated face-to-face with the second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip. Next, the system uses the measured alignment to associate transmitter pads on the first chip with proximate receiver pads on the second chip. The system then selectively routes data signals to transmitter pads on the first chip so that the data signals are communicated through capacitive coupling to intended receiver pads in the second chip that are proximate to the transmitter pads.
摘要翻译：本发明的一个实施例提供一种系统，其电子地对准不同半导体芯片上的焊盘，以便于通过电容耦合在半导体芯片之间进行通信。该系统通过测量第一芯片和第二芯片之间的对准来工作，其中第一芯片与第二芯片面对面设置，使得第一芯片上的发射器焊盘与第二芯片上的接收器焊盘电容耦合。接下来，系统使用测量的对准来将第一芯片上的发射器焊盘与第二芯片上的接近焊盘相关联。然后，系统选择性地将数据信号路由到第一芯片上的发射机焊盘，使得数据信号通过电容耦合传递到靠近发射器焊盘的第二芯片中的预期接收器焊盘。

5. 发明授权

US5123095A Integrated scalar and vector processors with vector addressing by the scalar processor 失效
标题翻译：具有标量处理器的向量寻址的集成标量和向量处理器
公开(公告)号：US5123095A
公开(公告)日：1992-06-16
申请号：US297981
申请日：1989-01-17
申请人： Gregory M. Papadopoulos , David E. Culler , James T. Pinkerton
发明人： Gregory M. Papadopoulos , David E. Culler , James T. Pinkerton
IPC分类号： G06F9/315 , G06F9/345 , G06F9/38 , G06F12/10 , G06F15/78 , G06F17/16
CPC分类号： G06F9/30032 , G06F15/8061 , G06F17/16 , G06F9/30036 , G06F9/3455 , G06F9/3877 , G06F12/1027
摘要： A vector processor is closely integrated with a scalar processor. The scalar processor provides virtual-to-physical memory translation for both scalar and vector operations. In vector operations, a block move operation preformed by the scalar processor is intercepted, the write command in the operation is converted to a read, and data resulting from a vector operation is returned to the address specified by the block move write command. Writing of the data may be masked by a prior vector operation. Prefetch queues and write queues are provided between main memory and the vector processor. A microinstruction interface is supported for the vector processor.
摘要翻译：矢量处理器与标量处理器紧密集成。标量处理器为标量和向量操作提供虚拟到物理内存转换。在矢量运算中，由标量处理器执行的块移动操作被截取，操作中的写入命令被转换为读取，并且由向量操作产生的数据返回到由块移动写命令指定的地址。数据的写入可能被先前的向量操作掩蔽。在主存储器和向量处理器之间提供预取队列和写队列。向量处理器支持微指令界面。

6. 发明授权

US5430850A Data processing system with synchronization coprocessor for multiple threads 失效
标题翻译：具有多线程同步协处理器的数据处理系统
公开(公告)号：US5430850A
公开(公告)日：1995-07-04
申请号：US734252
申请日：1991-07-22
申请人： Gregory M. Papadopoulos , Rishiyur S. Nikhil , Robert J. Greiner , Arvind
发明人： Gregory M. Papadopoulos , Rishiyur S. Nikhil , Robert J. Greiner , Arvind
IPC分类号： G06F9/46 , G06F9/48 , G06F9/52 , G06F15/16 , G06F15/177 , G06F15/82 , G06F15/80
CPC分类号： G06F9/4843 , G06F9/3009 , G06F9/3851
摘要： A multiprocessor system comprises a plurality of processing nodes, each node processing multiple threads of computation. Each node includes a data processor which sequentially processes blocks of code, each block defining a thread of computation. The code includes instructions to send start messages with data values to start new threads of computation. Each node also includes a synchronization coprocessor for processing start messages from the same and other nodes of the system. The coprocessor processes the start messages to store values as operands for threads of computation, to determine when all operands required for a thread of computation have been received and to provide an indication to the data processor that a thread of computation may be initiated. The data processor subsequently nonsynchronously initiates the thread of computation. Preferably, the processors load and store from and to a common memory with the translation from a local virtual address to a local physical address. The data processor creates messages to remote nodes using a global virtual address which is translated before transmission to a node designation and a local virtual address at the remote node. The synchronization coprocessor is a pipeline processor in which a data cache stage is modified to increment and test a counter value during a join operation.
摘要翻译：多处理器系统包括多个处理节点，每个节点处理多个计算线程。每个节点包括顺序地处理代码块的数据处理器，每个块定义计算线程。该代码包括用数据值发送开始消息以启动新的计算线程的指令。每个节点还包括用于处理来自系统的相同节点和其他节点的起始消息的同步协处理器。协处理器处理开始消息以将值存储为计算线程的操作数，以确定何时接收到计算线程所需的所有操作数，并向数据处理器提供可能启动计算线程的指示。数据处理器随后非同步地启动计算线程。优选地，处理器通过从本地虚拟地址到本地物理地址的转换来加载和存储公共存储器。数据处理器使用在传输到节点指定之前转换的全局虚拟地址和远程节点上的本地虚拟地址来向远程节点创建消息。同步协处理器是一个流水线处理器，其中在连接操作期间修改数据高速缓存阶段以递增和测试计数器值。

7. 发明授权

US5386586A System and method for construction of lists of deferred service requests 失效
标题翻译：用于构建延期服务请求列表的系统和方法
公开(公告)号：US5386586A
公开(公告)日：1995-01-31
申请号：US176497
申请日：1993-12-28
申请人： Gregory M. Papadopoulos
发明人： Gregory M. Papadopoulos
IPC分类号： G06F9/46 , G06F9/44 , G06F12/00 , G06F15/82
CPC分类号： G06F9/4436
摘要： In a data processing system, multiple requests for a service are stored on a deferred list formed out of already allocated memory space. Specifically, a received service request is added to the deferred list by altering the request as dictated by a stated convention. Preferably, the convention mandates that an instruction pointer of the received service request is decremented or otherwise manipulated. The altered received service request then is exchanged for a sevice request currently held at the service. The altering and exhanging are performed atomically. The service request that was previously held for the service is sent to the head of the current deferred list. It is preferred that the deferred list be formed out of activation frames.
摘要翻译：在数据处理系统中，对服务的多个请求存储在由已经分配的存储器空间形成的延迟列表上。具体地说，通过根据规定的约定来修改请求，将接收到的服务请求添加到延迟列表中。优选地，该约定要求接收的服务请求的指令指针递减或以其他方式操纵。然后，更改的接收到的服务请求被交换为当前在服务中保持的服务请求。改变和伸出原子地进行。先前为该服务持有的服务请求将发送到当前延期列表的头部。优选地，延迟列表由激活帧形成。

8. 发明授权

US5935249A Mechanism for embedding network based control systems in a local network interface device 失效
标题翻译：将网络控制系统嵌入本地网络接口设备的机制
公开(公告)号：US5935249A
公开(公告)日：1999-08-10
申请号：US806327
申请日：1997-02-26
申请人： Hal L. Stern , Gregory M. Papadopoulos
发明人： Hal L. Stern , Gregory M. Papadopoulos
IPC分类号： G06F1/00 , G06F21/00 , H04L29/06 , G06F12/14
CPC分类号： H04L63/0281 , G06F21/62 , G06F21/85 , H04L29/06 , H04L63/08 , H04L63/1408 , G06F2207/7219
摘要： A secure, trusted network management function embedded within a network interface device is provided. The network interface device connects a host computer to a network and contains a host bus interface, a network interface, and control logic. The network interface device incorporates a secure language processor, non-volatile memory, and a carrier sense circuit. The secure language processor executes a secure language program, and the non-volatile memory stores identification keys for remote devices and objects of value for network applications. If an application program is to be executed or accessed by the host computer, the secure language processor verifies that the object of value allows such execution or access. If a remote network device attempts to control the functionality of the network interface device, the secure language processor verifies that the remote network device has the authority to issue such a command.
摘要翻译：提供了嵌入在网络接口设备内的安全可靠的网络管理功能。网络接口设备将主计算机连接到网络，并包含主机总线接口，网络接口和控制逻辑。网络接口设备包含安全语言处理器，非易失性存储器和载波检测电路。安全语言处理器执行安全语言程序，并且非易失性存储器存储远程设备的识别密钥和用于网络应用的有价值的对象。如果应用程序要由主机执行或访问，则安全语言处理器验证该值的对象允许这样的执行或访问。如果远程网络设备尝试控制网络接口设备的功能，则安全语言处理器验证远程网络设备有权发出此类命令。

9. 发明授权

US5560029A Data processing system with synchronization coprocessor for multiple threads 失效
标题翻译：具有多线程同步协处理器的数据处理系统
公开(公告)号：US5560029A
公开(公告)日：1996-09-24
申请号：US185783
申请日：1994-05-31
申请人： Gregory M. Papadopoulos , Rishiyur S. Nikhil , Robert J. Greiner , Arvind
发明人： Gregory M. Papadopoulos , Rishiyur S. Nikhil , Robert J. Greiner , Arvind
IPC分类号： G06F9/46 , G06F9/48 , G06F9/52 , G06F15/16 , G06F15/177 , G06F15/82 , G06F15/80
CPC分类号： G06F9/4843 , G06F9/3009 , G06F9/3851
摘要： A multiprocessor system comprises a plurality of processing nodes, each node processing multiple threads of computation. Each node includes a data processor which sequentially processes blocks of code, each block defining a thread of computation. The code includes instructions to send start messages with data values to start new threads of computation. Each node also includes a synchronization coprocessor for processing start messages from the same and other nodes of the system. The coprocessor processes the messages from a message queue to store values as operands for threads of computation, to determine when all operands required for a thread of computation have been received and to provide in a continuation queue an indication to the data processor that a thread of computation may be initiated. The data processor subsequently nonsynchronously initiates the thread of computation. Alternatively, a single processor may perform the continuation and message processing functions in an interleaved sequence. The data processor creates messages to remote nodes using a global virtual address which is translated before transmission to a node designation and a local virtual address at the remote node.
摘要翻译： PCT No.PCT / US92 / 06150 Sec。 371日期1994年5月31日 102（e）日期1994年5月31日PCT提交1992年7月21日PCT公布。出版物WO93 / 02414 日期1993年2月4日多处理器系统包括多个处理节点，每个节点处理多个计算线程。每个节点包括顺序地处理代码块的数据处理器，每个块定义计算线程。该代码包括发送具有数据值的开始消息以开始新的计算线程的指令。每个节点还包括用于处理来自系统的相同节点和其他节点的起始消息的同步协处理器。协处理器处理来自消息队列的消息以将值存储为用于计算线程的操作数，以确定何时接收到计算线程所需的所有操作数，并在连续队列中向数据处理器提供指示线程可以开始计算。数据处理器随后非同步地启动计算线程。或者，单个处理器可以在交错序列中执行连续和消息处理功能。数据处理器使用在传输到节点指定之前转换的全局虚拟地址和远程节点上的本地虚拟地址来向远程节点创建消息。

10. 发明授权

US5412799A Efficient data processor instrumentation for systematic program debugging and development 失效
标题翻译：高效的数据处理器仪表，用于系统的程序调试和开发
公开(公告)号：US5412799A
公开(公告)日：1995-05-02
申请号：US41908
申请日：1993-04-02
申请人： Gregory M. Papadopoulos
发明人： Gregory M. Papadopoulos
IPC分类号： G06F9/44 , G06F11/34 , G06F15/82
CPC分类号： G06F11/34 , G06F8/45
摘要： A program is first analyzed in an ideal environment that assumes infinite processing resources and zero communication latency. In this environment, the program is viewed as being comprised of a plurality of steps of computation. Each step of computation is defined as the set of instructions that have all their operands available at that time. As such, each step of computation is limited only by data dependencies. The number of instructions executed for each step of computation is counted by the data processing system. The count of instructions may be used to produce an ideal parallelism profile that produces a graphical representation of the simulation. Having established an ideal level of parallelism in the ideal environment, a more realistic profile of the maximum level of parallelism may be obtained through analusis that accounts for a finite number of processors and for communication latency. This more realistic simulation is compared to the actual level of parallelism experienced when the program is executed. Should the comparison reveal room for improvement the program is tuned to resolve problems of work distribution and contention. of processors that process tokens; comprising the step of:a) inserting in with other tokens barrier token that causes statistics maintained by the processors to be sampled and available for output;b) processing the other tokens; andc) processing the barrier token to generate the sampling of the statistics.
摘要翻译：首先在一个假设无限的处理资源和零通信延迟的理想环境中分析一个程序。在这种环境中，该程序被视为由多个计算步骤组成。计算的每个步骤被定义为当时具有所有操作数可用的指令集。因此，每个计算步骤仅受数据依赖性限制。每个计算步骤执行的指令数由数据处理系统计数。可以使用指令计数来产生理想的平行度轮廓，其产生模拟的图形表示。在理想环境中建立了一个理想的平行度，通过解决有限数量的处理器和通信延迟的分析，可以获得更加真实的并行度水平。将这个更逼真的仿真与执行程序时遇到的实际并行度进行比较。如果比较显示改进空间，该方案将调整解决工作分配和争用的问题。处理令牌的处理器; 包括以下步骤：a）插入导致待处理器维护的统计数据被采样并可用于输出的其他令牌屏障令牌; b）处理其他令牌; 和c）处理障碍令牌以产生统计的采样。

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