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1. 发明申请

US20060026299A1 Communication among partitioned devices 有权
标题翻译：分区设备之间的通信
公开(公告)号：US20060026299A1
公开(公告)日：2006-02-02
申请号：US10902341
申请日：2004-07-29
申请人： Gary Gostin , Larry McMahan , Michael Schroeder , Craig Warner , Richard Adkisson , Huai-Ter Chong , David Binford , Mark Shaw , Joe Cowan , Thierry Fevrier , Arad Rostampour
发明人： Gary Gostin , Larry McMahan , Michael Schroeder , Craig Warner , Richard Adkisson , Huai-Ter Chong , David Binford , Mark Shaw , Joe Cowan , Thierry Fevrier , Arad Rostampour
IPC分类号： G06F15/16
CPC分类号： G06F9/5077 , G06F9/544 , G06F15/167
摘要： A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.
摘要翻译：公开了一种具有分区的计算设备和分区之间的通信方法，其中至少一个分区包括：至少一个寄存器，其基本上总是可被其他分区访问并且能够定义地址区域; 至少一个地址区域，其可以由其他分区访问并且能够由所述至少一个寄存器定义; 以及除了其他分区不可访问的至少一个可访问地址区域以外的地址区域。一种处理中断的方法，包括接收中断，根据其来源评估中断的起始点，接受，拒绝或进一步评估中断，当进一步评估中断时，根据其中的内容接受或拒绝中断，以及转发接受的中断但不拒绝对目标处理器的中断，并且还公开了执行该方法的设备。

2. 发明申请

US20050154810A1 Processor interrupt filtering 失效
标题翻译：处理器中断过滤
公开(公告)号：US20050154810A1
公开(公告)日：2005-07-14
申请号：US10756434
申请日：2004-01-12
申请人： Huai-Ter Chong , Gary Gostin , Craig Warner
发明人： Huai-Ter Chong , Gary Gostin , Craig Warner
IPC分类号： G06F9/48 , G06F12/00
CPC分类号： G06F9/4812
摘要： A method for processing an interrupt message in a system having a plurality of processors arranged into at least two partitions. The interrupt message is decoded to identify an interrupt source. If the interrupt source is not in an interrupt set, the interrupt is dropped. If the interrupt source is in a local partition, the interrupt is delivered. If the interrupt source is in the interrupt set and not in the local partition, the interrupt is processed in accordance with at least one of a target enable register and a vector enable register.
摘要翻译：一种在具有布置在至少两个分区中的多个处理器的系统中处理中断消息的方法。中断消息被解码以识别中断源。如果中断源不在中断集中，则中断被中断。如果中断源在本地分区中，则中断被传递。如果中断源处于中断集合而不在本地分区中，则根据目标使能寄存器和向量使能寄存器中的至少一个来处理中断。

3. 发明申请

US20050152390A1 Distribution of communications between paths 失效
标题翻译：路径之间的通信分配
公开(公告)号：US20050152390A1
公开(公告)日：2005-07-14
申请号：US10756668
申请日：2004-01-12
申请人： Michael Schroeder , Craig Warner , Gary Gostin , Mark Shaw
发明人： Michael Schroeder , Craig Warner , Gary Gostin , Mark Shaw
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/00 , H04L45/24
摘要： Distributing communications between paths, comprises providing a plurality of destinations, providing a plurality of communications paths such that each of the plurality of destinations can be accessed over each of the plurality of communications paths, defining destination addresses interleaved over the plurality of destinations, sending communications from a source to a plurality of the interleaved addresses, and selecting different ones of the plurality of paths for successive communications that are sent to addresses on different destinations, wherein the path for a communication is selected using at least a part of the address of the communication.
摘要翻译：分布路径之间的通信包括提供多个目的地，提供多个通信路径，使得可以通过多个通信路径中的每一个访问多个目的地中的每一个，定义在多个目的地上交织的目的地地址，发送通信从源到多个交错地址，以及选择多个路径中的不同路径用于连续通信，所述连续通信被发送到不同目的地上的地址，其中，使用至少一部分地址选择通信的路径通讯。

4. 发明申请

US20060026443A1 Communication among partitioned devices 有权
标题翻译：分区设备之间的通信
公开(公告)号：US20060026443A1
公开(公告)日：2006-02-02
申请号：US10902362
申请日：2004-07-29
申请人： Larry McMahan , Gary Gostin , Joe Cowan , Michael Krause
发明人： Larry McMahan , Gary Gostin , Joe Cowan , Michael Krause
IPC分类号： G06F12/14
CPC分类号： G06F12/0284 , G06F12/1441
摘要： A computing device having partitions, and a method of communicating between partitions, are disclosed wherein each partition comprises at least one address area readable but not writable from the other of the at least two partitions. In one embodiment one partition sends to the other partition a request for information, which information is in the other partition in an address area not accessible to the one partition, the other partition copies the information to an address area accessible to the one partition, and the one partition reads the information from the accessible address area. In another embodiment the at least one accessible address area of each partition includes a data area and a consumer pointer indicating the position to which that partition has read the data area in another partition.
摘要翻译：公开了一种具有分区的计算设备和分区之间的通信方法，其中每个分区包括至少一个地址区域，所述至少一个地址区域可从该至少两个分区中的另一个分区读取但不能写入。在一个实施例中，一个分区向另一个分区发送对信息的请求，哪个信息在一个分区不可访问的地址区域中的另一个分区中，另一个分区将该信息复制到该分区可访问的地址区域，以及一个分区从可访问的地址区域读取信息。在另一个实施例中，每个分区的至少一个可访问地址区域包括指示该分区已经读取另一个分区中的数据区域的位置的数据区和消费者指针。

5. 发明申请

US20050154881A1 Security measures in a partitionable computing system 有权
标题翻译：可分区计算系统中的安全措施
公开(公告)号：US20050154881A1
公开(公告)日：2005-07-14
申请号：US10756597
申请日：2004-01-12
申请人： Mark Shaw , Vipul Grandhi , Gary Gostin , Craig Warner
发明人： Mark Shaw , Vipul Grandhi , Gary Gostin , Craig Warner
IPC分类号： G06F21/00 , H04L9/00
CPC分类号： G06F21/53 , G06F2221/2105 , G06Q20/027
摘要： Methods and apparatus in a partitionable computing system. A processor communicates with a packet former. The packet former can be configured to construct a data packet that can include security status information related to a partition or processor.
摘要翻译：可分区计算系统中的方法和装置。处理器与数据包形成器通信。分组形成器可以被配置为构建可以包括与分区或处理器相关的安全状态信息的数据分组。

6. 发明申请

US20050154869A1 Security measures in a partitionable computing system 失效
标题翻译：可分区计算系统中的安全措施
公开(公告)号：US20050154869A1
公开(公告)日：2005-07-14
申请号：US10756702
申请日：2004-01-12
申请人： Mark Shaw , Vipul Gandhi , Leon Hong , Gary Gostin , Craig Warner , Paul Bouchier , Todd Kjos , Guy Kuntz , Richard Powers , Bryan Stephenson , Ryan Weaver , Brian Johnson , Glen Edwards , Brendan Voge , Gregg Lesartre
发明人： Mark Shaw , Vipul Gandhi , Leon Hong , Gary Gostin , Craig Warner , Paul Bouchier , Todd Kjos , Guy Kuntz , Richard Powers , Bryan Stephenson , Ryan Weaver , Brian Johnson , Glen Edwards , Brendan Voge , Gregg Lesartre
IPC分类号： G06F15/177 , G06F9/00 , G06F9/50 , G06F11/00 , G06F15/00 , G06F15/173 , G06F21/20 , G06F21/22 , H04L29/06
CPC分类号： H04L63/104 , G06F9/5077
摘要： A partitionable computer system and method of operating the same is disclosed. The partitionable computer system has a state machine, a processor, and a device controller. The state machine can be configured to monitor the status of a partition of the partitionable computer system. The information provided by the state machine can be used to provide security within the partitionable computing system.
摘要翻译：公开了一种可分割计算机系统及其操作方法。可分割计算机系统具有状态机，处理器和设备控制器。可以将状态机配置为监视可分区计算机系统的分区的状态。状态机提供的信息可用于在可分区计算系统内提供安全性。

7. 发明申请

US20050154910A1 Security measures in a partitionable computing system 审中-公开
标题翻译：可分区计算系统中的安全措施
公开(公告)号：US20050154910A1
公开(公告)日：2005-07-14
申请号：US10756705
申请日：2004-01-12
申请人： Mark Shaw , Vipul Gandhi , Leon Hong , Gary Gostin , Craig Warner
发明人： Mark Shaw , Vipul Gandhi , Leon Hong , Gary Gostin , Craig Warner
IPC分类号： G06F21/00 , H04L9/00
CPC分类号： G06F21/57 , G06F2221/2105
摘要： Methods and apparatus in a partitionable computing system. A state machine monitors the status of a partition or processor system. The security status information can be communicated to a device controller to protect a register within the device controller.
摘要翻译：可分区计算系统中的方法和装置。状态机监视分区或处理器系统的状态。安全状态信息可以传送到设备控制器以保护设备控制器内的寄存器。

8. 发明申请

US20050039084A1 Decoded match circuit for performance counter 失效
标题翻译：性能计数器的解码匹配电路
公开(公告)号：US20050039084A1
公开(公告)日：2005-02-17
申请号：US10945056
申请日：2004-09-20
申请人： Richard Adkisson , Gary Gostin
发明人： Richard Adkisson , Gary Gostin
IPC分类号： H04B1/74
CPC分类号： G06F11/348 , G06F11/364 , G06F2201/88
摘要： A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match signal comprising logic for decoding a sum field comprising a selected portion of the data into a decoded_sum signal, wherein an active bit of the decoded_sum field corresponds to a value of the sum field; and logic for comparing the decoded_sum signal with a mask signal and outputting a binary bit comprising a decoded_match signal indicative of whether the decoded_sum signal and the mask signal match.
摘要翻译：描述连接到承载数据总线的匹配电路。在一个实施例中，匹配电路包括用于激活解码匹配信号的逻辑，用于激活解码匹配信号的逻辑，包括逻辑，用于将包括数据的选定部分的和字段解码为解码的信号，其中解码的字段的有效位对应于和字段的值; 以及用于将decode_sum信号与掩码信号进行比较并输出包括指示解码的信号和掩码信号是否匹配的解码匹配信号的二进制位的逻辑。

9. 发明申请

US20060023820A1 Controller for clock synchronizer 失效
标题翻译：时钟同步器控制器
公开(公告)号：US20060023820A1
公开(公告)日：2006-02-02
申请号：US10901773
申请日：2004-07-29
申请人： Richard Adkisson , Gary Gostin
发明人： Richard Adkisson , Gary Gostin
IPC分类号： H04L7/00
CPC分类号： H04L7/02
摘要： A controller arrangement and method for effectuating data transfer between a first clock domain and a second clock domain. In one embodiment, inversion circuitry inverts a first clock signal associated with the first clock domain into an inverted first clock signal that is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain. Clock synchronizer controller circuitry operates responsive to sampled sync pulses based on the SYNC pulse to generate domain synchronizer control signals for effectuating data transfer between the first and second clock domains.
摘要翻译：一种用于在第一时钟域和第二时钟域之间实现数据传送的控制器布置和方法。在一个实施例中，反相电路将与第一时钟域相关联的第一时钟信号反相为反相第一时钟信号，该反相第一时钟信号用于在反相第一时钟信号的重合边沿期间产生SYNC脉冲，以及与第二时钟相关联的第二时钟信号域。时钟同步器控制器电路响应于基于SYNC脉冲的采样同步脉冲来产生域同步器控制信号，用于实现第一和第二时钟域之间的数据传输。

10. 发明申请

US20060023819A1 Clock synchronizer 审中-公开
标题翻译：时钟同步器
公开(公告)号：US20060023819A1
公开(公告)日：2006-02-02
申请号：US10901762
申请日：2004-07-29
申请人： Richard Adkisson , Gary Gostin , Christopher Greer
发明人： Richard Adkisson , Gary Gostin , Christopher Greer
IPC分类号： H04L7/00
CPC分类号： H04L7/0012
摘要： A clock synchronizer for effectuating data transfer between first and second clock domains by utilizing first and second synchronizer controllers. The first synchronizer controller circuit operates in the first clock domain which has N first clock cycles and the second synchronizer controller circuit operates in the second clock domain which has M second clock cycles, wherein N/M≧1. Inversion circuitry inverts a first clock signal associated with the first clock domain to generate an inverted first clock signal which is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain.
摘要翻译：一种时钟同步器，用于通过利用第一和第二同步器控制器来实现第一和第二时钟域之间的数据传输。第一同步器控制器电路在具有N个第一时钟周期的第一时钟域中工作，并且第二同步器控制器电路在具有M个第二时钟周期的第二时钟域中工作，其中N / M> = 1。反相电路将与第一时钟域相关联的第一时钟信号反相以产生反相的第一时钟信号，其用于在反相的第一时钟信号的重合边沿和与第二时钟域相关联的第二时钟信号中实现SYNC脉冲。

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