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1. 发明授权

US07840863B2 Functional frequency testing of integrated circuits 失效
公开(公告)号：US07840863B2
公开(公告)日：2010-11-23
申请号：US12635068
申请日：2009-12-10
申请人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
发明人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
IPC分类号： G01R31/28 , G06F1/12 , G06F1/00
CPC分类号： G01R31/318555 , G01R31/318541 , H03K3/35625
摘要： A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

2. 发明申请

US20100088562A1 FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS 失效
标题翻译：集成电路的功能频率测试
公开(公告)号：US20100088562A1
公开(公告)日：2010-04-08
申请号：US12635122
申请日：2009-12-10
申请人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
发明人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318555 , G01R31/318541 , H03K3/35625
摘要： A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.
摘要翻译：一种用于通过提供测试控制器产生控制信号的测试控制器的方法和电路，所述控制信号确保在测试器频率下扫描链中的测试图案的正确锁存，并且通过在功能时钟频率下测试的逻辑电路来传播测试图案。

3. 发明授权

US07290191B2 Functional frequency testing of integrated circuits 失效
标题翻译：集成电路的功能频率测试
公开(公告)号：US07290191B2
公开(公告)日：2007-10-30
申请号：US10711075
申请日：2004-08-20
申请人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
发明人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
IPC分类号： G01R31/28
CPC分类号： G01R31/318555 , G01R31/318541 , H03K3/35625
摘要： A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.
摘要翻译：一种用于通过提供测试控制器产生控制信号的测试控制器的方法和电路，所述控制信号确保在测试器频率下扫描链中的测试图案的正确锁存，并且通过在功能时钟频率下测试的逻辑电路来传播测试图案。

4. 发明授权

US07840864B2 Functional frequency testing of integrated circuits 失效
公开(公告)号：US07840864B2
公开(公告)日：2010-11-23
申请号：US12635122
申请日：2009-12-10
申请人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
发明人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
IPC分类号： G01R31/28 , G06F1/12 , G06F1/00
CPC分类号： G01R31/318555 , G01R31/318541 , H03K3/35625
摘要： A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

5. 发明申请

US20100088561A1 FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS 失效
公开(公告)号：US20100088561A1
公开(公告)日：2010-04-08
申请号：US12635068
申请日：2009-12-10
申请人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
发明人： Gary D. Grise , Steven F. Oakland , Anthony D. Polson , Philip S. Stevens
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318555 , G01R31/318541 , H03K3/35625
摘要： A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

6. 发明授权

US09075106B2 Detecting chip alterations with light emission 有权
标题翻译：用光发射检测芯片变化
公开(公告)号：US09075106B2
公开(公告)日：2015-07-07
申请号：US12512168
申请日：2009-07-30
申请人： Kerry Bernstein , James Culp , David F. Heidel , Dirk Pfeiffer , Anthony D. Polson , Peilin Song , Franco Stellari , Robert L. Wisnieff
发明人： Kerry Bernstein , James Culp , David F. Heidel , Dirk Pfeiffer , Anthony D. Polson , Peilin Song , Franco Stellari , Robert L. Wisnieff
IPC分类号： G06K9/00 , G01R31/311 , G01R31/00
CPC分类号： G01R31/311
摘要： An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.
摘要翻译：通过测量要测试的物理电路来获得待测试电路的发射图。通过测量物理参考电路或通过模拟从参考电路预期的发射来获得参考电路的发射图。与参考电路相比，要测试的电路的发射图与参考电路的发射图进行比较，以确定待测电路中的变化的存在。

7. 发明申请

US20090228843A1 METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT 失效
标题翻译：通过调节选择性电压激活切割点来优化功率的方法
公开(公告)号：US20090228843A1
公开(公告)日：2009-09-10
申请号：US12041729
申请日：2008-03-04
申请人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests the operating speeds and power consumption levels of the integrated circuit devices. Then, the method adjusts the initial cut point to a final cut point based on the testing, to minimize the maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices.
摘要翻译：在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路和相对较快的集成电路器件。该方法选择初始操作速度切割点以使相对较慢的集成电路和相对快速的集成电路器件的最大功率电平最小化。然后，该方法使用集成电路设计制造集成电路器件，并测试集成电路器件的工作速度和功耗水平。然后，该方法基于测试将初始切割点调整到最终切割点，以使相对较慢的集成电路和相对较快的集成电路器件的最大功率电平最小化。

8. 发明授权

US07418689B2 Method of generating wiring routes with matching delay in the presence of process variation 有权
标题翻译：在存在过程变化的情况下生成具有匹配延迟的布线路线的方法
公开(公告)号：US07418689B2
公开(公告)日：2008-08-26
申请号：US10908102
申请日：2005-04-27
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

9. 发明授权

US07890906B2 Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells 有权
标题翻译：基于单个电池的已知多晶硅周边密度布置集成电路设计的方法
公开(公告)号：US07890906B2
公开(公告)日：2011-02-15
申请号：US12117761
申请日：2008-05-09
申请人： Laura S. Chadwick , James A. Culp , David J. Hathaway , Anthony D. Polson
发明人： Laura S. Chadwick , James A. Culp , David J. Hathaway , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.
摘要翻译：公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

10. 发明授权

US07849433B2 Integrated circuit with uniform polysilicon perimeter density, method and design structure 有权
标题翻译：具有均匀多晶硅周密度的集成电路，方法和设计结构
公开(公告)号：US07849433B2
公开(公告)日：2010-12-07
申请号：US12117771
申请日：2008-05-09
申请人： Laura S. Chadwick , James A. Culp , David J Hathaway , Anthony D. Polson
发明人： Laura S. Chadwick , James A. Culp , David J Hathaway , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5072
摘要： Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.
摘要翻译：公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。这种重新配置以基本维持期望的去耦电容的方式执行。由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。

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