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1. 发明授权

US07668037B2 Storage array including a local clock buffer with programmable timing 有权
标题翻译：存储阵列包括具有可编程时序的本地时钟缓冲器
公开(公告)号：US07668037B2
公开(公告)日：2010-02-23
申请号：US11935566
申请日：2007-11-06
申请人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/14 , G11C29/50 , G11C29/50012
摘要： A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaluate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.
摘要翻译：包括具有可编程时序的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。本地时钟缓冲器可以独立调节控制字线和本地位线预充电脉冲的本地时钟的脉冲宽度以及控制全局位线预充电，评估和读取数据锁存的延迟时钟的脉冲宽度。本地时钟和延迟时钟之间的延迟也可以调整。通过改变本地和延迟的时钟信号的脉冲宽度以及时钟间延迟，可以通过读取和写入具有变化的脉冲宽度和时钟延迟的单元来评估阵列中每个单元的定时裕度。所得到的评估可用于评估管芯内的时间裕度变化，以及在管芯到管芯之间以及在变化的环境（例如电压和温度变化）下的变化。

2. 发明授权

US07409305B1 Pulsed ring oscillator circuit for storage cell read timing evaluation 有权
标题翻译：脉冲环形振荡电路用于存储单元读取时序评估
公开(公告)号：US07409305B1
公开(公告)日：2008-08-05
申请号：US11682542
申请日：2007-03-06
申请人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G06F3/01
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A methor for storage cell read timing evaluation provides read strength information by using a pulsed ring oscillator. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译：用于存储单元读取定时评估的方法通过使用脉冲环形振荡器来提供读取强度信息。脉冲发生器耦合到待测量的存储单元连接到的位线。因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。读取电流是电流之间的差异。

3. 发明授权

US07620510B2 Pulsed ring oscillator circuit for storage cell read timing evaluation 有权
标题翻译：脉冲环形振荡电路用于存储单元读取时序评估
公开(公告)号：US07620510B2
公开(公告)日：2009-11-17
申请号：US12128526
申请日：2008-05-28
申请人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G06F3/00
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译：用于存储单元读取定时评估的脉冲环形振荡器电路提供读取强度信息。脉冲发生器耦合到待测量的存储单元连接到的位线。因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。读取电流是电流之间的差异。

4. 发明授权

US07880507B2 Circular edge detector 失效
标题翻译：圆形边缘检测器
公开(公告)号：US07880507B2
公开(公告)日：2011-02-01
申请号：US12621763
申请日：2009-11-19
申请人： Jerry C Kao , Jente B Kuang , Alan J Drake , Gary D Carpenter , Fadi H Gebara
发明人： Jerry C Kao , Jente B Kuang , Alan J Drake , Gary D Carpenter , Fadi H Gebara
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译：在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及状态捕捉块可操作地连接以接收当前信元信号。将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

5. 发明授权

US07564739B2 Storage cell design evaluation circuit including a wordline timing and cell access detection circuit 失效
标题翻译：存储单元设计评估电路，包括字线定时和单元访问检测电路
公开(公告)号：US07564739B2
公开(公告)日：2009-07-21
申请号：US12125011
申请日：2008-05-21
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Kai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Kai Ngo
IPC分类号： G11C8/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路提供关于静态存储单元中的状态变化的精确信息。存储单元测试行包括访问检测电路，其在与阵列中的其他单元的访问操作期间提供相同的负载。访问检测电路提供可以探测的输出，而不影响单元的定时，读取稳定性或可写性。测试行可以测试行的时钟和/或地址时序，并且可以包括用于行字线驱动器的单独的电源轨，从而可以确定访问时序，读取稳定性和可写入性与字线强度/访问电压的变化。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

6. 发明申请

US20080137455A1 Storage Cell Design Evaluation Circuit Including a Wordline Timing and Cell Access Detection Circuit 失效
标题翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路
公开(公告)号：US20080137455A1
公开(公告)日：2008-06-12
申请号：US11609598
申请日：2006-12-12
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：用于存储单元设计评估的方法提供关于静态存储单元中的状态变化的准确信息。字线选择脉冲沿着测试行的字线选择路径传播到输出驱动器电路，以便测试该行的时钟和/或地址时序，使得访问时序，读取稳定性和可写性与字线强度的变化 /访问电压可以确定。访问检测单元保持输出驱动器电路的输入，直到由字线选择脉冲激活的模拟访问操作完成。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

7. 发明授权

US07995418B2 Method and computer program for controlling a storage device having per-element selectable power supply voltages 有权
标题翻译：用于控制具有每元件可选电源电压的存储装置的方法和计算机程序
公开(公告)号：US07995418B2
公开(公告)日：2011-08-09
申请号：US12399551
申请日：2009-03-06
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元素可选择的电源电压来控制存储设备的方法和计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

8. 发明授权

US07551508B2 Energy efficient storage device using per-element selectable power supply voltages 失效
标题翻译：使用每元件可选电源电压的节能存储设备
公开(公告)号：US07551508B2
公开(公告)日：2009-06-23
申请号：US11941168
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：使用每元件可选择的电源电压的节能存储装置在保持特定的性能水平的同时在存储装置中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

9. 发明授权

US07414904B2 Method for evaluating storage cell design using a wordline timing and cell access detection circuit 失效
标题翻译：使用字线定时和单元访问检测电路评估存储单元设计的方法
公开(公告)号：US07414904B2
公开(公告)日：2008-08-19
申请号：US11609598
申请日：2006-12-12
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：用于存储单元设计评估的方法提供关于静态存储单元中的状态变化的准确信息。字线选择脉冲沿着测试行的字线选择路径传播到输出驱动器电路，以便测试该行的时钟和/或地址时序，使得访问时序，读取稳定性和可写性与字线强度的变化 /访问电压可以确定。访问检测单元保持输出驱动器电路的输入，直到由字线选择脉冲激活的模拟访问操作完成。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

10. 发明授权

US08208339B2 Computer program product for controlling a storage device having per-element selectable power supply voltages 有权
标题翻译：用于控制具有每元件可选电源电压的存储装置的计算机程序产品
公开(公告)号：US08208339B2
公开(公告)日：2012-06-26
申请号：US13115149
申请日：2011-05-25
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元件可选择的电源电压来控制存储设备的计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

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