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1. 发明授权

US07471623B2 Systems and methods for a unified computer system fabric 有权
标题翻译：统一计算机系统架构的系统和方法
公开(公告)号：US07471623B2
公开(公告)日：2008-12-30
申请号：US10998239
申请日：2004-11-23
申请人： Gary B. Gostin , Craig Warner , John W. Bockhaus
发明人： Gary B. Gostin , Craig Warner , John W. Bockhaus
IPC分类号： H04L1/00
CPC分类号： G06F13/4022
摘要： Disclosed are systems and methods providing a unified system fabric in a computer. The systems and methods of embodiments including first interface disposed between a first component of the computer system and a second component of the computer system, the first interface implementing an interface protocol, and a second interface disposed between the first component of the computer system and a third component of the computer system, the second interface implementing the interface protocol, wherein the first interface and the second interface comprise separate signal paths at the first component.
摘要翻译：公开了在计算机中提供统一的系统结构的系统和方法。实施例的系统和方法包括设置在计算机系统的第一部件和计算机系统的第二部件之间的第一接口，实现接口协议的第一接口和设置在计算机系统的第一部件之间的第二接口和计算机系统的第三组件，实现接口协议的第二接口，其中第一接口和第二接口在第一组件处包括单独的信号路径。

2. 发明授权

US4620275A Computer system 失效
标题翻译：电脑系统
公开(公告)号：US4620275A
公开(公告)日：1986-10-28
申请号：US622451
申请日：1984-06-20
申请人： Steven J. Wallach , Thomas M. Jones , Frank J. Marshall , David A. Nobles , Kent A. Fuka , Steven M. Rowan , William H. Wallace , Harold W. Dozier , David M. Chastain , John W. Clark , Robert B. Kolstad , James E. Mankovich , Michael C. Harris , Jeffrey H. Gruger , Alan D. Gant , Harold D. Shelton , James R. Weatherford , Arthur T. Kimmel , Gary B. Gostin , Gilbert J. Hansen , John M. Golenbieski , Larry W. Spry , Gerald Matulka , Gaynel J. Lockhart , Michael E. Sydow
发明人： Steven J. Wallach , Thomas M. Jones , Frank J. Marshall , David A. Nobles , Kent A. Fuka , Steven M. Rowan , William H. Wallace , Harold W. Dozier , David M. Chastain , John W. Clark , Robert B. Kolstad , James E. Mankovich , Michael C. Harris , Jeffrey H. Gruger , Alan D. Gant , Harold D. Shelton , James R. Weatherford , Arthur T. Kimmel , Gary B. Gostin , Gilbert J. Hansen , John M. Golenbieski , Larry W. Spry , Gerald Matulka , Gaynel J. Lockhart , Michael E. Sydow
IPC分类号： G06F15/78 , G06F9/18
CPC分类号： G06F15/8069
摘要： A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor. In a further aspect of the computer there is produced an entry microword from a store for the immediate execution of the first microinstruction within a sequence of microinstructions. The remaining microinstructions are produced from a conventional store. This reduces the delay in the retrieval and execution of the first microinstruction. In a still further aspect of the computer there is included the logical data cache which stores data at logical addresses such that the central processor can store and retrieve data without the necessity of first making a translation from logical to physical address.
摘要翻译：矢量处理计算机被配置为以流水线方式操作，其中每个功能单元基本上是独立的并且被设计为以最快的方式执行其操作功能。矢量元素通过源总线从存储器，主存储器，物理缓存单元或逻辑高速缓存传送，其中元件被交替地加载到向量处理单元中。矢量控制单元解码矢量指令，并产生用于在矢量处理单元内操作寄存器和逻辑单元的所需控制命令。因此，矢量处理单元基本上并行地工作，使处理速率加倍。所得到的矢量通过目的地总线传送到物理高速缓存单元，主存储器，逻辑高速缓存或输入/输出处理器。在计算机的另一方面，产生了来自商店的入口微词，用于在微指令序列内立即执行第一微指令。剩余的微指令是从常规商店生产的。这减少了第一微指令的检索和执行的延迟。在计算机的另一方面，包括逻辑数据高速缓存，其以逻辑地址存储数据，使得中央处理器可以存储和检索数据，而不需要首先进行从逻辑地址到物理地址的转换。

3. 发明授权

US07568063B2 System and method for a distributed crossbar network using a plurality of crossbars 有权
标题翻译：一种使用多个十字条的分布式交叉网络的系统和方法
公开(公告)号：US07568063B2
公开(公告)日：2009-07-28
申请号：US11346041
申请日：2006-02-02
申请人： Gary B. Gostin , Mark E. Shaw
发明人： Gary B. Gostin , Mark E. Shaw
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F15/17337
摘要： A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X−1)/2], wherein X equals the number of processor clusters.
摘要翻译：公开了一种用于多处理系统中的多跳交叉的单跳，处理器到处理器通信的系统和方法。简要描述，一个实施例是包括具有多个高带宽点对点链路的多个处理器的多处理系统; 多个处理器集群，每个处理器集群具有驻留在其中的预定数量的处理器; 以及多个十字条，所述十字条中的一个将所述多个处理器群中的一个处理器的处理器中的每一个耦合到所述多个处理器群中的另一处理器群的每个处理器，使得所有处理器耦合到每个其他处理器，并且使得十字形的数量等于[X *（X-1）/ 2]，其中X等于处理器集群的数量。

4. 发明授权

US06959370B2 System and method for migrating data between memories 有权
标题翻译：用于在存储器之间迁移数据的系统和方法
公开(公告)号：US06959370B2
公开(公告)日：2005-10-25
申请号：US10336430
申请日：2003-01-03
申请人： Mark E. Shaw , Gary B. Gostin
发明人： Mark E. Shaw , Gary B. Gostin
IPC分类号： G06F12/06 , G06F12/08 , G06F12/00
CPC分类号： G06F12/08
摘要： An embodiment of the invention provides a method for migrating data from one location to another comprising establishing a new memory location under control of a specific memory accessing device. The new memory location being where data, which is being migrated from a first memory location, is to be resident, the specific accessing device taking control of a certain portion of data resident at the first memory location, the control preventing the certain data from being accessed by any device other than the specific accessing device, obtaining, under control of the specific accessing device, a most recent version of the certain data from the first memory location, forwarding the obtained certain data to the new memory location, and when the obtained certain data is forwarded to the new memory location, marking the certain data as being gone from the first memory location such that attempts to access the certain data at the first memory location from a specific accessing device will be redirected back to the accessing device for redirection to the new memory location.
摘要翻译：本发明的实施例提供了一种用于将数据从一个位置迁移到另一个位置的方法，包括在特定存储器访问设备的控制下建立新的存储器位置。正在从第一存储器位置迁移的数据将被驻留的新存储器位置，特定访问设备控制驻留在第一存储器位置的某一部分数据，该控制防止某些数据被由特定访问设备以外的任何设备访问，在特定访问设备的控制下，获取来自第一存储器位置的特定数据的最新版本，将获得的特定数据转发到新的存储器位置，并且当获得某些数据被转发到新的存储器位置，将某些数据标记为从第一存储器位置移除，使得从特定访问设备访问第一存储器位置处的某些数据的尝试将被重定向回到访问设备以进行重定向到新的内存位置。

5. 发明授权

US5832290A Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems 失效
标题翻译：用于改进矢量处理系统中存储器带宽利用率的装置，系统和方法
公开(公告)号：US5832290A
公开(公告)日：1998-11-03
申请号：US785192
申请日：1997-01-17
申请人： Gary B. Gostin , Matthew F. Barr , Ruth A. McGuffey , Russell L. Roan
发明人： Gary B. Gostin , Matthew F. Barr , Ruth A. McGuffey , Russell L. Roan
IPC分类号： G06F9/345 , G06F15/78 , G06F12/00
CPC分类号： G06F9/30098 , G06F15/8076 , G06F9/345
摘要： Vector register circuitry is provided which includes a vector register file comprising at least one vector register having a plurality of elements, the vector register file further having at least one data port and at least one address port for accessing selected ones of the elements of the vector register. Address generation circuitry is provided coupled to the address port and includes an adder having an output coupled to the address port, a first element register having an output coupled to a first input of the adder and an element counter having an output coupled to a second input of the adder.
摘要翻译：提供了矢量寄存器电路，其包括矢量寄存器文件，该矢量寄存器文件包括至少一个具有多个元素的向量寄存器，向量寄存器文件还具有至少一个数据端口和至少一个地址端口用于访问向量中的所选元素寄存器。提供地址产生电路，其耦合到地址端口并且包括具有耦合到地址端口的输出的加法器，具有耦合到加法器的第一输入的输出的第一元件寄存器和具有耦合到第二输入的输出的元件计数器的加法器。

6. 发明授权

US5050070A Multi-processor computer system having self-allocating processors 失效
标题翻译：具有自分配处理器的多处理器计算机系统
公开(公告)号：US5050070A
公开(公告)日：1991-09-17
申请号：US161768
申请日：1988-02-29
申请人： David M. Chastain , James E. Mankovich , Gary B. Gostin
发明人： David M. Chastain , James E. Mankovich , Gary B. Gostin
IPC分类号： G06F9/44 , G06F9/46 , G06F9/50 , G06F15/167 , G06F15/173
CPC分类号： G06F15/167 , G06F15/173 , G06F9/3004 , G06F9/30087 , G06F9/3009 , G06F9/3834 , G06F9/5066 , G06F9/52
摘要： A computer system comprises a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available. However, if all processors are busy, then the processor conducting the serial operation will also execute all of the parallel operations. Thus, the processors are self-allocated, rather than being used on a demand or master-servant basis. This permits a greater throughput for the system because processors are not held idle when there is available process work to be done.

7. 发明授权

US07908422B2 System and method for a distributed crossbar network using a plurality of crossbars 有权
标题翻译：一种使用多个十字条的分布式交叉网络的系统和方法
公开(公告)号：US07908422B2
公开(公告)日：2011-03-15
申请号：US12481628
申请日：2009-06-10
申请人： Gary B. Gostin , Mark E. Shaw
发明人： Gary B. Gostin , Mark E. Shaw
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F15/17337
摘要： A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X−1)/2], wherein X equals the number of processor clusters.
摘要翻译：公开了一种用于多处理系统中的多跳交叉的单跳，处理器到处理器通信的系统和方法。简要描述，一个实施例是包括具有多个高带宽点对点链路的多个处理器的多处理系统; 多个处理器集群，每个处理器集群具有驻留在其中的预定数量的处理器; 以及多个十字条，所述十字条中的一个将所述多个处理器群中的一个处理器的处理器中的每一个耦合到所述多个处理器群中的另一处理器群的每个处理器，使得所有处理器耦合到每个其他处理器，并且使得十字形的数量等于[X *（X-1）/ 2]，其中X等于处理器集群的数量。

8. 发明授权

US07475302B2 Decoded match circuit for performance counter 失效
标题翻译：性能计数器的解码匹配电路
公开(公告)号：US07475302B2
公开(公告)日：2009-01-06
申请号：US10945056
申请日：2004-09-20
申请人： Richard W. Adkisson , Gary B. Gostin
发明人： Richard W. Adkisson , Gary B. Gostin
IPC分类号： G01R31/28 , G06F13/36
CPC分类号： G06F11/348 , G06F11/364 , G06F2201/88
摘要： A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match signal comprising logic for decoding a sum field comprising a selected portion of the data into a decoded_sum signal, wherein an active bit of the decoded_sum field corresponds to a value of the sum field; and logic for comparing the decoded_sum signal with a mask signal and outputting a binary bit comprising a decoded_match signal indicative of whether the decoded_sum signal and the mask signal match.
摘要翻译：描述连接到承载数据总线的匹配电路。在一个实施例中，匹配电路包括用于激活解码匹配信号的逻辑，用于激活解码匹配信号的逻辑，包括逻辑，用于将包括数据的选定部分的和字段解码为解码的信号，其中解码的字段的有效位对应于和字段的值; 以及用于将decode_sum信号与掩码信号进行比较并输出包括指示解码的信号和掩码信号是否匹配的解码匹配信号的二进制位的逻辑。

9. 发明授权

US5649144A Apparatus, systems and methods for improving data cache hit rates 失效
标题翻译：用于提高数据高速缓存命中率的装置，系统和方法
公开(公告)号：US5649144A
公开(公告)日：1997-07-15
申请号：US705023
申请日：1996-08-29
申请人： Gary B. Gostin , Gregory D. Brinson , Todd H. Beck , David L. Trawick
发明人： Gary B. Gostin , Gregory D. Brinson , Todd H. Beck , David L. Trawick
IPC分类号： G06F9/312 , G06F12/08 , G06F13/00
CPC分类号： G06F9/30043 , G06F12/0862 , G06F2212/6026
摘要： A processing system is provided which generates a memory address and presents the memory address to a cache to retrieve corresponding data when such corresponding data is encached therein. The memory address is presented to a main memory to retrieve the corresponding data therefrom when such corresponding data is not encached in cache. An offset address to the memory address is used to obtain a prefetch address which in turn is presented to the main memory to retrieve selected information stored within memory. The cache then stores the selected information retrieved from the main memory.
摘要翻译：提供了一种处理系统，其产生存储器地址并将存储器地址呈现给高速缓存以在这样的对应数据被附加在其中时检索对应的数据。当这种对应的数据未被加入到高速缓存中时，存储器地址被呈现给主存储器以从其中检索相应的数据。使用存储器地址的偏移地址来获得预取地址，该预取地址又被呈现给主存储器以检索存储在存储器内的所选信息。然后，高速缓存存储从主存储器检索的所选信息。

10. 发明授权

US5159686A Multi-processor computer system having process-independent communication register addressing 失效
标题翻译：具有独立于进程的通信寄存器寻址的多处理器计算机系统
公开(公告)号：US5159686A
公开(公告)日：1992-10-27
申请号：US666038
申请日：1991-03-07
申请人： David M. Chastain , James E. Mankovich , Gary B. Gostin
发明人： David M. Chastain , James E. Mankovich , Gary B. Gostin
IPC分类号： G06F9/44 , G06F9/46 , G06F9/50 , G06F15/167 , G06F15/78
CPC分类号： G06F9/5066 , G06F15/167 , G06F15/8053 , G06F9/52
摘要： A computer system having a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available. However, if all processors are busy, then the processor conducting the serial operation will also execute all of the parallel operations. Thus, the processors are self-allocated, rather than being used on a demand or master-servant basis. This permits a greater throughput for the system because processors are not held idle when there is available process work to be done.
摘要翻译：具有多个独立处理器的计算机系统，其可以为每个处理器执行单独的处理，或者对于一个进程跨多个处理器执行并行处理操作。计算机系统包括被分成一组帧的一组通信寄存器和分别对应于寄存器的一组信号。典型的进程具有串行和并行代码段。在串行执行期间，一个进程由单个处理器执行，但是当遇到并行指令时，表示可以并行执行代码，发布信号量以邀请其他处理器并行执行进程。如果系统中的任何其他处理器处于空闲状态，则这些处理器将检测信号量并接受进程操作线程。如果有足够的操作可用，两个或多个处理器可以并行运行。然而，如果所有处理器都忙，则进行串行操作的处理器也将执行所有并行操作。因此，处理器是自分配的，而不是在需求或主服务器上使用。这允许系统更大的吞吐量，因为当有可用的处理工作要完成时，处理器不会保持空闲状态。

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