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1. 发明授权

US4620275A Computer system 失效
标题翻译：电脑系统
公开(公告)号：US4620275A
公开(公告)日：1986-10-28
申请号：US622451
申请日：1984-06-20
申请人： Steven J. Wallach , Thomas M. Jones , Frank J. Marshall , David A. Nobles , Kent A. Fuka , Steven M. Rowan , William H. Wallace , Harold W. Dozier , David M. Chastain , John W. Clark , Robert B. Kolstad , James E. Mankovich , Michael C. Harris , Jeffrey H. Gruger , Alan D. Gant , Harold D. Shelton , James R. Weatherford , Arthur T. Kimmel , Gary B. Gostin , Gilbert J. Hansen , John M. Golenbieski , Larry W. Spry , Gerald Matulka , Gaynel J. Lockhart , Michael E. Sydow
发明人： Steven J. Wallach , Thomas M. Jones , Frank J. Marshall , David A. Nobles , Kent A. Fuka , Steven M. Rowan , William H. Wallace , Harold W. Dozier , David M. Chastain , John W. Clark , Robert B. Kolstad , James E. Mankovich , Michael C. Harris , Jeffrey H. Gruger , Alan D. Gant , Harold D. Shelton , James R. Weatherford , Arthur T. Kimmel , Gary B. Gostin , Gilbert J. Hansen , John M. Golenbieski , Larry W. Spry , Gerald Matulka , Gaynel J. Lockhart , Michael E. Sydow
IPC分类号： G06F15/78 , G06F9/18
CPC分类号： G06F15/8069
摘要： A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor. In a further aspect of the computer there is produced an entry microword from a store for the immediate execution of the first microinstruction within a sequence of microinstructions. The remaining microinstructions are produced from a conventional store. This reduces the delay in the retrieval and execution of the first microinstruction. In a still further aspect of the computer there is included the logical data cache which stores data at logical addresses such that the central processor can store and retrieve data without the necessity of first making a translation from logical to physical address.
摘要翻译：矢量处理计算机被配置为以流水线方式操作，其中每个功能单元基本上是独立的并且被设计为以最快的方式执行其操作功能。矢量元素通过源总线从存储器，主存储器，物理缓存单元或逻辑高速缓存传送，其中元件被交替地加载到向量处理单元中。矢量控制单元解码矢量指令，并产生用于在矢量处理单元内操作寄存器和逻辑单元的所需控制命令。因此，矢量处理单元基本上并行地工作，使处理速率加倍。所得到的矢量通过目的地总线传送到物理高速缓存单元，主存储器，逻辑高速缓存或输入/输出处理器。在计算机的另一方面，产生了来自商店的入口微词，用于在微指令序列内立即执行第一微指令。剩余的微指令是从常规商店生产的。这减少了第一微指令的检索和执行的延迟。在计算机的另一方面，包括逻辑数据高速缓存，其以逻辑地址存储数据，使得中央处理器可以存储和检索数据，而不需要首先进行从逻辑地址到物理地址的转换。

2. 发明授权

US4873629A Instruction processing unit for computer 失效
标题翻译：电脑指令处理单元
公开(公告)号：US4873629A
公开(公告)日：1989-10-10
申请号：US133195
申请日：1987-12-15
申请人： Michael C. Harris , David M. Chastain , Gary B. Gostin
发明人： Michael C. Harris , David M. Chastain , Gary B. Gostin
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3808 , G06F9/3822
摘要： A computer (20) is configured for optimizing the processing rate of instructions and the throughput of data. The computer (20) includes a main memory (99), a memory control unit (22), a physical cache unit (100), and a central processor (156). A instruction processing unit (126) is included within the central processor (156). The function of the instruction processing unit (126) is to decode instructions and produce instruction execution commands or directing the execution of the instructions within the central processor (156). Instructions are transferred from the main memory (99) into a register (180) where the address fields of the instructions are decoded to produce a cracked instruction and these instructions are stored in a logical instruction cache (210). As the cracked instructions are selected they are transferred to an output buffer and decoder (214) where the remaining fields of the instructions are decoded to produce instruction execution commands. The instructions in the cache (210) are stored at logical rather than at physical addresses. The cache (210) further can operate at double the rate of a basic clock period for the computer (20) such that a branch instruction can be selected in one clock cycle. The combination of the logical instructiion cache (210) and the concurrent computation of program counts serves to substantially increase the instruction execution rate for the computer (20).
摘要翻译：计算机（20）被配置为优化指令的处理速率和数据的吞吐量。计算机（20）包括主存储器（99），存储器控制单元（22），物理高速缓存单元（100）和中央处理器（156）。指令处理单元（126）包括在中央处理器（156）内。指令处理单元（126）的功能是解码指令并产生指令执行命令或指示中央处理器（156）内的指令的执行。指令从主存储器（99）传送到寄存器（180），其中指令的地址字段被解码以产生破解指令，并且这些指令被存储在逻辑指令高速缓存（210）中。当选择破解的指令时，它们被传送到输出缓冲器和解码器（214），其中指令的剩余字段被解码以产生指令执行命令。高速缓存（210）中的指令以逻辑而不是物理地址存储。高速缓存（210）还可以以计算机（20）的基本时钟周期的速率的两倍工作，使得可以在一个时钟周期中选择分支指令。逻辑指令高速缓存（210）和程序计数的并发计算的组合用于大大增加计算机（20）的指令执行率。

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