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1. 发明授权

US08726113B2 Selective per-cycle masking of scan chains for system level test 有权
标题翻译：用于系统级测试的扫描链选择性每周期屏蔽
公开(公告)号：US08726113B2
公开(公告)日：2014-05-13
申请号：US13453929
申请日：2012-04-23
申请人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
摘要翻译：用于处理未知状态问题的集成电路的内置自检技术。一些实现使用与时间压缩器相连的专用扫描链选择器。专门的扫描链选择器的存在提高了掩蔽X状态的效率。还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3）以处理过度掩蔽现象。

2. 发明授权

US08347159B2 Compression based on deterministic vector clustering of incompatible test cubes 有权
标题翻译：基于不兼容测试立方体的确定性向量聚类的压缩
公开(公告)号：US08347159B2
公开(公告)日：2013-01-01
申请号：US12718813
申请日：2010-03-05
申请人： Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
发明人： Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G06F11/00
CPC分类号： G01R31/31921 , G01R31/318547
摘要： The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.
摘要翻译：测试数据压缩方案基于确定性向量聚类。在存在冲突的情况下，具有许多类似指定位的测试立方体将合并到父模式中。父模式以及表示冲突位的控制模式和增量模式被有效地编码。三模式解压缩器可用于解压缩测试数据。

3. 发明申请

US20120210181A1 SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST 有权
标题翻译：用于系统级测试的扫描链的选择性周期性掩蔽
公开(公告)号：US20120210181A1
公开(公告)日：2012-08-16
申请号：US13453929
申请日：2012-04-23
申请人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
摘要翻译：用于处理未知状态问题的集成电路的内置自检技术。一些实现使用与时间压缩器相连的专用扫描链选择器。专门的扫描链选择器的存在提高了掩蔽X状态的效率。还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3）以处理过度掩蔽现象。

4. 发明授权

US08166359B2 Selective per-cycle masking of scan chains for system level test 有权
标题翻译：用于系统级测试的扫描链选择性每周期屏蔽
公开(公告)号：US08166359B2
公开(公告)日：2012-04-24
申请号：US12341996
申请日：2008-12-22
申请人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
摘要翻译：用于处理未知状态问题的集成电路的内置自检技术。一些实现使用与时间压缩器相连的专用扫描链选择器。专门的扫描链选择器的存在提高了掩蔽X状态的效率。还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3）以处理过度掩蔽现象。

5. 发明授权

US08832512B2 Low power compression of incompatible test cubes 有权
标题翻译：不兼容的测试立方体的低功率压缩
公开(公告)号：US08832512B2
公开(公告)日：2014-09-09
申请号：US13049829
申请日：2011-03-16
申请人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
发明人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
IPC分类号： G06F11/00
CPC分类号： G06F11/079
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.
摘要翻译：公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。可以通过产生低切换控制模式来进一步降低功耗。

6. 发明申请

US20110231721A1 LOW POWER COMPRESSION OF INCOMPATIBLE TEST CUBES 有权
标题翻译：低功耗压缩不完全测试
公开(公告)号：US20110231721A1
公开(公告)日：2011-09-22
申请号：US13049829
申请日：2011-03-16
申请人： DARIUSZ CZYSZ , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
发明人： DARIUSZ CZYSZ , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
IPC分类号： G06F11/00 , G06F1/32
CPC分类号： G06F11/079
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.
摘要翻译：公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。可以通过产生低切换控制模式来进一步降低功耗。

7. 发明申请

US20100229060A1 Compression Based On Deterministic Vector Clustering Of Incompatible Test Cubes 有权
标题翻译：基于不相容性测试立方体的确定性矢量聚类的压缩
公开(公告)号：US20100229060A1
公开(公告)日：2010-09-09
申请号：US12718813
申请日：2010-03-05
申请人： GRZEGORZ MRUGALSKI , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
发明人： GRZEGORZ MRUGALSKI , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31921 , G01R31/318547
摘要： The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.
摘要翻译：测试数据压缩方案基于确定性向量聚类。在存在冲突的情况下，具有许多类似指定位的测试立方体将合并到父模式中。父模式以及表示冲突位的控制模式和增量模式被有效地编码。三模式解压缩器可用于解压缩测试数据。

8. 发明授权

US08290738B2 Low power scan testing techniques and apparatus 有权
标题翻译：低功耗扫描测试技术和设备
公开(公告)号：US08290738B2
公开(公告)日：2012-10-16
申请号：US13049844
申请日：2011-03-16
申请人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
发明人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
IPC分类号： G06F19/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（EDT）架构）集成）。在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可以用于产生用于与任何所公开的实施例一起使用的测试图案的示例性测试图形生成方法。

9. 发明申请

US20100138708A1 DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS 有权
标题翻译：用于测试模式的低功率分解的分解器
公开(公告)号：US20100138708A1
公开(公告)日：2010-06-03
申请号：US12641150
申请日：2009-12-17
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

10. 发明授权

US08046653B2 Low power decompression of test cubes 有权
标题翻译：测试立方体的低功率减压
公开(公告)号：US08046653B2
公开(公告)日：2011-10-25
申请号：US12854786
申请日：2010-08-11
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31921 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

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