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1. 发明专利

CA2582345A1 SIGMA-DELTA BASED PHASE LOCK LOOP 未知
公开(公告)号：CA2582345A1
公开(公告)日：2006-04-13
申请号：CA2582345
申请日：2005-09-21
申请人： GCT SEMICONDUCTOR INC
发明人： PARK JOONBAE , KOO YIDO , AHN YOUNGHO , LEE JEONG-WOO , SONG EUNSEOK , LEE KYEONGHO
IPC分类号： H03D3/24
摘要： A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

2. 发明专利

AU2003284893A8 System and method for suppressing noise in a phase-locked loop circuit 未知
公开(公告)号：AU2003284893A8
公开(公告)日：2004-05-25
申请号：AU2003284893
申请日：2003-10-23
申请人： GCT SEMICONDUCTOR INC
发明人： KOO YIDO , PARK JOONBAE , LEE JEONG-WOO , SONG EUNSEOK , AHN YOUNGHO , LEE KYEONGHO
IPC分类号： H03L7/197 , H03L7/06
摘要： A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

3. 发明专利

CA2582345C SIGMA-DELTA BASED PHASE LOCK LOOP 未知
公开(公告)号：CA2582345C
公开(公告)日：2013-11-05
申请号：CA2582345
申请日：2005-09-21
申请人： GCT SEMICONDUCTOR INC
发明人： KOO YIDO , AHN YOUNGHO , SONG EUNSEOK , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
IPC分类号： H03D3/24
摘要： A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PDF to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

4. 发明专利

HK1082351A1 COMMUNICATION TRANSMITTER USING OFFSET PHASE-LOCKED-LOOP 未知
公开(公告)号：HK1082351A1
公开(公告)日：2006-06-02
申请号：HK06104363
申请日：2006-04-11
申请人： GCT SEMICONDUCTOR INC
发明人： LEE KANG-YOON , SONG EUNSEOK , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
IPC分类号： H03C3/09 , H04L20100101
摘要： A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. In still other embodiments, a transmitter signal is generated without using any phase-locked-loop circuits. This is accomplished by generating an intermediate frequency signal using a crystal oscillator, and then using a frequency divider in a feedback loop to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. By minimizing the number of phase-locked-loop circuits in the transmitter, the size, cost, and power requirements of mobile handsets may be significantly reduced.

5. 发明专利

AU2003284892A1 RADIO RECEIVER AND METHOD FOR AM SUPPRESSION AND DC-OFFSET REMOVAL 未知
公开(公告)号：AU2003284892A1
公开(公告)日：2004-05-25
申请号：AU2003284892
申请日：2003-10-23
申请人： GCT SEMICONDUCTOR INC
发明人： PARK JOONBAE , LEE KYEONGHO , SONG EUNSEOK , JUNG YEONJAE
IPC分类号： H04B1/10
摘要： A communications receiver includes a baseband signal recovery circuit which uses a low-IF architecture for data reception. The baseband signal recovery circuit uses a full-analog implementation for channel selection and filtering. Thus, the overhead placed on the design of analog-to-digital converter is greatly relaxed and most of hardware can be re-used for multi-mode applications with only a slight modification.

6. 发明专利

CA2503055A1 RADIO RECEIVER AND METHOD FOR AM SUPPRESSION AND DC-OFFSET REMOVAL 未知
公开(公告)号：CA2503055A1
公开(公告)日：2004-05-13
申请号：CA2503055
申请日：2003-10-23
申请人： GCT SEMICONDUCTOR INC
发明人： SONG EUNSEOK , LEE KYEONGHO , JUNG YEONJAE , PARK JOON-BAE
IPC分类号： H04B1/10 , H04L25/10
摘要： A communications receiver includes a baseband signal recovery circuit (4) which uses a low-IF architecture for data reception. The baseband signal recovery circuit uses a full-analog implementation for channel selection and filtering (5). Thus, the overhead placed on the design of analog-to-digital converter is greatly relaxed and most of hardware can be re-used for multi- mode applications with only a slight modification.

7. 发明专利

CA2502841A1 SYSTEM AND METHOD FOR SUPPRESSING NOISE IN A PHASE-LOCKED LOOP CIRCUIT 未知
公开(公告)号：CA2502841A1
公开(公告)日：2004-05-13
申请号：CA2502841
申请日：2003-10-23
申请人： GCT SEMICONDUCTOR INC
发明人： PARK JOONBAE , LEE JEONG-WOO , KOO YIDO , LEE KYEONGHO , AHN YOUNGHO , SONG EUNSEOK
IPC分类号： H03L7/197 , H03L7/06
摘要： A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase- locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

8. 发明专利

AU2003254188A1 AN RF FRONT END WITH REDUCED CARRIER LEAKAGE 未知
公开(公告)号：AU2003254188A1
公开(公告)日：2004-02-16
申请号：AU2003254188
申请日：2003-07-28
申请人： GCT SEMICONDUCTOR INC
发明人： LEE KYEONGHO , SONG EUNSEOK , LEE SEUNG-WOOK , LEE JEONG-WOO , PARK JOONBAE
IPC分类号： H04B1/28 , H04B1/52 , H04B1/00 , H04B1/26
摘要： A method and apparatus that provide a frequency conversion in a radio frequency front-end are disclosed, including a frequency divider that divides an input signal frequency by a predetermined value to produce an output signal frequency; and a frequency mixer that mixes the output signal frequency with a carrier signal frequency to produce a converted signal frequency, which is substantially equal to a difference between the output signal frequency and the carrier signal frequency. The predetermined value and the input signal frequency are selected such that the carrier signal frequency is not substantially equivalent to an integer multiple of the output signal frequency. The method and apparatus can be used in a wireless communication receiver including wireless communication systems and wireless LAN systems.

9. 发明专利

CA2442721A1 FRACTIONAL-N FREQUENCY SYNTHESIZER WITH FRACTIONAL COMPENSATION METHOD 未知
公开(公告)号：CA2442721A1
公开(公告)日：2002-09-26
申请号：CA2442721
申请日：2002-03-20
申请人： GCT SEMICONDUCTOR INC
发明人： SONG EUNSEOK , HUH HYUNGKI , LEE KANG YOON , KOO YIDO , PARK JOONBAE , LEE JEONGWOO , LEE KYEONGHO
IPC分类号： H03L7/087 , H03L7/089 , H03L7/091 , H03L7/093 , H03L7/095 , H03L7/197 , H04L7/033 , H04L7/00
摘要： A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phas e comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and- hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample - and-hold circuit.

10. 发明专利

DE60225426T2 未知
公开(公告)号：DE60225426T2
公开(公告)日：2009-03-12
申请号：DE60225426
申请日：2002-03-20
申请人： GCT SEMICONDUCTOR INC
发明人： HUH HYUNGKI , SONG EUNSEOK , LEE KANG YOON , KOO YIDO , LEE JEONGWOO , PARK JOONBAE , LEE KYEONGHO
IPC分类号： H04L7/00 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/093 , H03L7/095 , H03L7/197 , H04L7/033
摘要： A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.

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