专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06979621B2 Trench MOSFET having low gate charge 有权
标题翻译：沟槽MOSFET栅极电荷低
公开(公告)号：US06979621B2
公开(公告)日：2005-12-27
申请号：US10751687
申请日：2004-01-05
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/28185 , H01L21/28194 , H01L29/42368 , H01L29/4925 , H01L29/4933 , H01L29/511 , H01L29/513
摘要： A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.
摘要翻译：一种沟槽MOSFET器件，包括：（a）第一导电类型（优选N型导电性）的硅衬底; （b）在衬底上的第一导电类型的硅外延层，所述外延层具有比衬底更低的载流子浓度; （c）在所述外延层的上部内具有第二导电类型（优选P型导电性）的体区; （d）具有沟槽侧壁和沟槽底部的沟槽，其从外延层的上表面延伸到外延层并穿过器件的本体区域; （f）衬在所述沟槽上的氧化物区域，其包括覆盖至少所述沟槽底部的下部段和覆盖所述沟槽侧壁的至少上部区域的上段; （g）邻近氧化物区域的沟槽内的导电区域; 和（h）第一导电类型的源极区域，位于主体区域的上部并且与沟槽相邻。在本实施例中，氧化物区域的下段比氧化物区域的上部段更厚。

2. 发明授权

US06674124B2 Trench MOSFET having low gate charge 有权
标题翻译：沟槽MOSFET栅极电荷低
公开(公告)号：US06674124B2
公开(公告)日：2004-01-06
申请号：US10002529
申请日：2001-11-15
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L21/28185 , H01L21/28194 , H01L29/42368 , H01L29/4925 , H01L29/4933 , H01L29/511 , H01L29/513
摘要： A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.
摘要翻译：一种沟槽MOSFET器件，包括：（a）第一导电类型（优选N型导电性）的硅衬底; （b）在衬底上的第一导电类型的硅外延层，所述外延层具有比衬底更低的载流子浓度; （c）在所述外延层的上部内具有第二导电类型（优选P型导电性）的体区; （d）具有沟槽侧壁和沟槽底部的沟槽，其从外延层的上表面延伸到外延层并穿过器件的本体区域; （f）衬在所述沟槽上的氧化物区域，其包括覆盖至少所述沟槽底部的下部段和覆盖所述沟槽侧壁的至少上部区域的上段; （g）邻近氧化物区域的沟槽内的导电区域; 和（h）第一导电类型的源极区域，位于主体区域的上部并且与沟槽相邻。在本实施例中，氧化物区域的下段比氧化物区域的上部段更厚。

3. 发明授权

US06657255B2 Trench DMOS device with improved drain contact 有权
标题翻译：沟槽DMOS器件具有改善的漏极接触
公开(公告)号：US06657255B2
公开(公告)日：2003-12-02
申请号：US10021419
申请日：2001-10-30
申请人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/41741 , H01L29/41766 , H01L29/7809 , H01L29/7811
摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.
摘要翻译：一种沟槽DMOS晶体管器件，其包括：（a）第一导电类型的衬底; （b）在所述衬底上的第一导电类型的外延层，其中所述外延层具有比所述衬底更低的载流子浓度; （c）从外延层的上表面延伸到外延层中的沟槽; （d）衬在所述沟槽的至少一部分上的绝缘层; （e）邻近绝缘层的沟槽内的导电区域; （f）设置在所述外延层的上部并且与所述沟槽相邻的第二导电类型的体区; （g）第一导电类型的源区域，位于本体区域的上部并且与沟槽相邻; 和（h）从外延层的上表面延伸到器件中的一个或多个低电阻率深区域。低电阻率深区用于与衬底电接触，衬底是衬底的共用漏极区。通过以这种方式构造沟槽DMOS晶体管器件，源极，漏极和栅极触点都可以设置在器件的单个表面上。

4. 发明授权

US06548860B1 DMOS transistor structure having improved performance 有权
标题翻译： DMOS晶体管结构具有改进的性能
公开(公告)号：US06548860B1
公开(公告)日：2003-04-15
申请号：US09515335
申请日：2000-02-29
申请人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0626 , H01L29/0865 , H01L29/1095 , H01L29/7811
摘要： A trench DMOS transistor structure is provided that includes at least three individual trench DMOS transistor cells formed on a substrate of a first conductivity type. The plurality of individual DMOS transistor cells is dividable into peripheral transistor cells and interior transistor cells. Each of the individual transistor cells includes a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. A conductive electrode is located in the trench, which overlies the insulating layer. Interior transistor cells, but not the peripheral transistor cells, each further include a source region of the first conductivity type in the body region adjacent to the trench.
摘要翻译：提供沟槽DMOS晶体管结构，其包括形成在第一导电类型的衬底上的至少三个单独沟槽DMOS晶体管单元。多个独立的DMOS晶体管单元可分为外围晶体管单元和内部晶体管单元。每个单独的晶体管单元包括位于基板上的体区，其具有第二导电类型。至少一个沟槽延伸穿过身体区域和衬底。绝缘层对沟槽进行排列。导电电极位于沟槽中，覆盖绝缘层。内部晶体管单元，但不是外围晶体管单元，每个还包括与沟槽相邻的体区中的第一导电类型的源极区域。

5. 发明授权

US06518621B1 Trench DMOS transistor having reduced punch-through 有权
公开(公告)号：US06518621B1
公开(公告)日：2003-02-11
申请号：US09395790
申请日：1999-09-14
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4916
摘要： A method of forming a trench DMOS transistor is provides which reduces punch-through. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

6. 发明授权

US06312993B1 High speed trench DMOS 有权
标题翻译：高速沟DMOS
公开(公告)号：US06312993B1
公开(公告)日：2001-11-06
申请号：US09515749
申请日：2000-02-29
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4916 , H01L29/4925 , H01L29/4933
摘要： A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.
摘要翻译：提供了制造沟槽DMOS的方法，其利用多硅化物和难熔技术来制造出具有低栅极电阻，低栅极电容，降低的分布式RC栅极传播延迟以及用于高频应用的改进的开关速度的沟槽DMOS。

7. 发明授权

US6025230A High speed MOSFET power device with enhanced ruggedness fabricated by simplified processes 失效
标题翻译：高速MOSFET功率器件，通过简化的工艺制造出增强的耐用性
公开(公告)号：US6025230A
公开(公告)日：2000-02-15
申请号：US965349
申请日：1997-11-06
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21/336 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/78 , H01L21/76
CPC分类号： H01L29/402 , H01L29/42372 , H01L29/66712 , H01L29/7802 , H01L29/7813 , H01L29/0638
摘要： This invention discloses a MOSFET power device supported on a substrate. The MOSFET power device includes a plurality polysilicon-with-oxide-cap segments disposed over a gate oxide layer including two outermost segments and a plurality of inner segments include a plurality of gate oxide-plug openings. Each of the inner segments functions as agate and the two outer most segments function as a field plate and an equal potential ring separated by a termination oxide-plug gap and the gate oxide-plug openings and the termination oxide-plug gap having an aspect ratio greater or equal to 0.5. The MOSFET power device further includes a plurality of MOSFET transistor cells for each of the gates, wherein each transistor cells further includes a source region, a body region, the transistor cells further having a common drain disposed at a bottom surface of the substrate. Each of the inner segments functions as a gate having a side wall spacer surrounding edges of the inner segments, and the gate oxide-plug openings and the termination oxide-plug gap being filled with an oxide plug. The MOSFET transistor cells are covered by an overlying insulation layer having a plurality of contact openings defined therein. The MOSFET power device further includes a plurality of metal segments covering the overlying insulation layer and being in electric contact with the DMOS device through the contact opening. The MOSFET power device further includes a plurality of deep-and-narrow gaps between the metal segments wherein each gap having an aspect ratio equal to or greater than 0.5.
摘要翻译：本发明公开了一种支撑在基板上的MOSFET功率器件。 MOSFET功率器件包括设置在包括两个最外部段的栅极氧化物层之上的多个多晶硅 - 氧化物 - 盖段，并且多个内部段包括多个栅极氧化物 - 塞子开口。每个内部区段用作玛瑙，并且两个最外面的区段用作场板和由终止氧化物 - 塞子间隙分开的等电位环，并且栅极氧化物 - 塞子开口和终止氧化物 - 塞子间隙具有纵横比大于或等于0.5。 MOSFET功率器件还包括用于每个栅极的多个MOSFET晶体管单元，其中每个晶体管单元还包括源极区域，体区域，晶体管单元还具有布置在衬底底表面处的共同漏极。每个内部区段用作具有围绕内部段的边缘的侧壁间隔件的栅极，并且栅极氧化物 - 塞子开口和终止氧化物 - 塞子间隙填充有氧化物塞。 MOSFET晶体管单元由其上限定有多个接触开口的上覆绝缘层覆盖。 MOSFET功率器件还包括覆盖上覆绝缘层的多个金属段，并通过接触开口与DMOS器件电接触。 MOSFET功率器件还包括在金属段之间的多个深而窄的间隙，其中每个间隙具有等于或大于0.5的纵横比。

8. 发明授权

US5877529A Mosfet termination design and core cell configuration to increase breakdown voltage and to improve device ruggedness 失效
标题翻译： Mosfet终端设计和核心单元配置，以增加击穿电压并提高器件的耐用性
公开(公告)号：US5877529A
公开(公告)日：1999-03-02
申请号：US978667
申请日：1997-11-26
申请人： Koon Chong So , Danny Chi Nim , Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Shu-Hui Cheng
发明人： Koon Chong So , Danny Chi Nim , Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Shu-Hui Cheng
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L29/76 , H01L23/58 , H01L29/94
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/7811 , H01L29/0696 , H01L2924/0002
摘要： Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve higher breakdown voltage and improved device ruggedness. The power transistor includes a core cell area which includes a plurality of power transistor cells and a termination area. The power transistor further includes an outer pickup guarding ring, disposed in the termination area guarding the core cell area, for picking up free charged-particles generated in the termination area for preventing the free charged particles from entering the core cell area. In another preferred embodiment, the power transistor further includes an inner pickup guarding fence and blocks, disposed between the termination area and the core cell area for picking up free charged-particles not yet picked up by the outer pickup guarding ring for preventing the free charged particles from entering the core cell area.
摘要翻译：在本发明中公开了改进的功率MOSFET结构和制造工艺，以实现更高的击穿电压和改进的器件耐用性。功率晶体管包括包含多个功率晶体管单元和端接区域的核心单元区域。功率晶体管还包括外部拾波器保护环，设置在保护核心单元区域的端接区域中，用于拾取终止区域中产生的免费带电粒子，以防止自由带电粒子进入核心单元区域。在另一个优选实施例中，功率晶体管还包括内部拾取器防护栅栏和块，其设置在终端区域和核心单元区域之间，用于拾取由外部拾音器保护环尚未拾取的免费带电粒子，以防止自由充电颗粒进入核心区域。

9. 发明授权

US07364994B2 Method for manufacturing a superjunction device with wide mesas 失效
标题翻译：制造具有宽台面的超级结装置的方法
公开(公告)号：US07364994B2
公开(公告)日：2008-04-29
申请号：US11420490
申请日：2006-05-26
申请人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
IPC分类号： H01L21/425 , H01L21/336 , H01L21/332 , H01L21/44 , H01L23/58
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66712 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
摘要翻译：制造半导体器件的方法包括提供具有沟槽和台面的半导体衬底。至少一个台面具有第一和第二侧壁。该方法包括将第二导电性的掺杂剂角度地注入到第一侧壁中，并将第二导电性的掺杂剂角度地注入第二侧壁。通过将掺杂剂扩散到至少一个台面中，将至少一个台面转变成柱。然后通过将第一导电性的掺杂剂角度地注入到柱的第一侧壁中，并且将第一导电类型的掺杂剂角度地注入到柱的第二侧壁中，将柱转换成列。然后将掺杂剂扩散到柱中以提供沿相邻沟槽的深度方向定位的第一和第二掺杂区的P-N结。最后，沟槽填充绝缘材料。

10. 发明授权

US07015125B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
公开(公告)号：US07015125B2
公开(公告)日：2006-03-21
申请号：US10983490
申请日：2004-11-08
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/8242
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式