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1. 发明授权

US06977203B2 Method of forming narrow trenches in semiconductor substrates 有权
标题翻译：在半导体衬底中形成窄沟槽的方法
公开(公告)号：US06977203B2
公开(公告)日：2005-12-20
申请号：US10010162
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/308 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/311 , H01L21/3205
CPC分类号： H01L21/3088 , H01L21/3086
摘要： A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.
摘要翻译：一种在半导体衬底内形成沟槽的方法。该方法例如包括以下：（a）提供半导体衬底; （b）提供在半导体衬底上具有第一孔的图案化的第一CVD沉积掩模材料层; （c）在所述第一掩蔽材料层上沉积第二CVD沉积的掩模材料层; （d）蚀刻所述第二掩模材料层，直到在所述第一孔径内的所述第二掩模材料中产生比所述第一孔径窄的第二孔径; 以及（e）通过所述第二孔蚀刻所述半导体衬底，使得在所述半导体衬底中形成沟槽。在优选实施例中，本发明的方法用于形成沟槽MOSFET器件。

2. 发明授权

US07364994B2 Method for manufacturing a superjunction device with wide mesas 失效
标题翻译：制造具有宽台面的超级结装置的方法
公开(公告)号：US07364994B2
公开(公告)日：2008-04-29
申请号：US11420490
申请日：2006-05-26
申请人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
IPC分类号： H01L21/425 , H01L21/336 , H01L21/332 , H01L21/44 , H01L23/58
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66712 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
摘要翻译：制造半导体器件的方法包括提供具有沟槽和台面的半导体衬底。至少一个台面具有第一和第二侧壁。该方法包括将第二导电性的掺杂剂角度地注入到第一侧壁中，并将第二导电性的掺杂剂角度地注入第二侧壁。通过将掺杂剂扩散到至少一个台面中，将至少一个台面转变成柱。然后通过将第一导电性的掺杂剂角度地注入到柱的第一侧壁中，并且将第一导电类型的掺杂剂角度地注入到柱的第二侧壁中，将柱转换成列。然后将掺杂剂扩散到柱中以提供沿相邻沟槽的深度方向定位的第一和第二掺杂区的P-N结。最后，沟槽填充绝缘材料。

3. 发明授权

US07052982B2 Method for manufacturing a superjunction device with wide mesas 失效
标题翻译：制造具有宽台面的超级结装置的方法
公开(公告)号：US07052982B2
公开(公告)日：2006-05-30
申请号：US11017468
申请日：2004-12-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
IPC分类号： H01L21/425
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66712 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
摘要翻译：制造半导体器件的方法包括提供具有沟槽和台面的半导体衬底。至少一个台面具有第一和第二侧壁。该方法包括将第二导电性的掺杂剂角度地注入到第一侧壁中，并将第二导电性的掺杂剂角度地注入第二侧壁。通过将掺杂剂扩散到至少一个台面中，将至少一个台面转变成柱。然后通过将第一导电性的掺杂剂角度地注入到柱的第一侧壁中，并且将第一导电类型的掺杂剂角度地注入到柱的第二侧壁中，将柱转换成列。然后将掺杂剂扩散到柱中以提供沿相邻沟槽的深度方向定位的第一和第二掺杂区的P-N结。最后，沟槽填充绝缘材料。

4. 发明授权

US06645815B2 Method for forming trench MOSFET device with low parasitic resistance 有权
公开(公告)号：US06645815B2
公开(公告)日：2003-11-11
申请号：US10010483
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L21/823487 , H01L29/1095 , Y10S148/126
摘要： A method is provided for forming shallow and deep dopant implants adjacent source regions of a first conductivity type within an upper portion of an epitaxial layer in a trench MOSFET device. The method comprises: (a) forming a patterned implantation mask over the epitaxial layer, wherein the patterned implantation mask comprises a patterned insulating region and covers at least a portion of the source regions, and wherein the patterned implantation mask has apertures over at least portions of the epitaxial layer adjacent the source regions; (b) forming shallow dopant regions by a process comprising: (1) implanting a first dopant of a second conductivity type at a first energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the first dopant at elevated temperatures to a first depth from an upper surface of the epitaxial layer; (c) forming deep dopant regions by a process comprising: (1) implanting a second dopant of the second conductivity type at a second energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the second dopant at elevated temperatures to a second depth from the upper surface of the epitaxial layer; and (d) enlarging apertures in the patterned insulating region. In this method, the second energy level is greater than the first energy level, the second depth is greater than the first depth, and the first and second dopants can be the same or different. The method of the present invention can be used, for example, to form a device that comprises a plurality of trench MOSFET cells.

5. 发明申请

US20080290442A1 PROCESS FOR HIGH VOLTAGE SUPERJUNCTION TERMINATION 审中-公开
公开(公告)号：US20080290442A1
公开(公告)日：2008-11-27
申请号：US12104131
申请日：2008-04-16
申请人： Fwu-Iuan Hshieh , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Brian D. Pratt
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/66712 , H01L21/26586 , H01L21/76251 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

6. 发明授权

US07772086B2 Process for high voltage superjunction termination 失效
标题翻译：高压超连接端接工艺
公开(公告)号：US07772086B2
公开(公告)日：2010-08-10
申请号：US12053067
申请日：2008-03-21
申请人： Fwu-Iuan Hshieh , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Brian D. Pratt
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L29/66712 , H01L21/26586 , H01L21/76251 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
摘要翻译：制造具有有源区和端接区的半导体器件的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。半导体衬底具有有源区和围绕有源区的端接区。第一主表面被氧化。在终端区域中形成第一多个沟槽和第一多个台面。终端区域中的第一多个沟槽被电介质材料填充。终端区域中的第二多个沟槽。第二多个沟槽与介电材料一起使用。

7. 发明申请

US20080166855A1 PROCESS FOR HIGH VOLTAGE SUPERJUNCTION TERMINATION 失效
标题翻译：高电压超级终止过程
公开(公告)号：US20080166855A1
公开(公告)日：2008-07-10
申请号：US12053062
申请日：2008-03-21
申请人： Fwu-Iuan Hshieh , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Brian D. Pratt
IPC分类号： H01L21/762
CPC分类号： H01L29/66712 , H01L21/26586 , H01L21/76251 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
摘要翻译：制造具有有源区和端接区的半导体器件的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。半导体衬底具有有源区和围绕有源区的端接区。第一主表面被氧化。在终端区域中形成第一多个沟槽和第一多个台面。终端区域中的第一多个沟槽用电介质材料填充。终端区域中的第二多个沟槽。第二多个沟槽与介电材料一起使用。

8. 发明授权

US07354818B2 Process for high voltage superjunction termination 失效
标题翻译：高压超连接端接工艺
公开(公告)号：US07354818B2
公开(公告)日：2008-04-08
申请号：US11318873
申请日：2005-12-27
申请人： Fwu-Iuan Hshieh , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Brian D. Pratt
IPC分类号： H01L21/8238
CPC分类号： H01L29/66712 , H01L21/26586 , H01L21/76251 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches are formed in the termination region. The trenches of the second plurality of trenches are filled with the dielectric material.
摘要翻译：制造具有有源区和端接区的半导体器件的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。半导体衬底具有有源区和围绕有源区的端接区。第一主表面被氧化。在终端区域中形成第一多个沟槽和第一多个台面。终端区域中的第一多个沟槽用电介质材料填充。在终端区域中形成第二多个沟槽。第二多个沟槽的沟槽用电介质材料填充。

9. 发明授权

US07759204B2 Process for high voltage superjunction termination 失效
公开(公告)号：US07759204B2
公开(公告)日：2010-07-20
申请号：US12053062
申请日：2008-03-21
申请人： Fwu-Iuan Hshieh , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Brian D. Pratt
IPC分类号： H01L21/336
CPC分类号： H01L29/66712 , H01L21/26586 , H01L21/76251 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

10. 发明申请

US20080283956A1 PROCESS FOR HIGH VOLTAGE SUPERJUNCTION TERMINATION 失效
公开(公告)号：US20080283956A1
公开(公告)日：2008-11-20
申请号：US12104137
申请日：2008-04-16
申请人： Fwu-Iuan Hshieh , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Brian D. Pratt
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/66712 , H01L21/26586 , H01L21/76251 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

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