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1. 发明授权

US5883850A Programmable logic array integrated circuits 失效
公开(公告)号：US5883850A
公开(公告)日：1999-03-16
申请号：US664919
申请日：1996-06-18
申请人： Fung Fung Lee , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Joseph Huang , Bahram Ahanin
发明人： Fung Fung Lee , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Joseph Huang , Bahram Ahanin
IPC分类号： G11C8/12 , H03K19/173 , H03K19/177 , G11C13/00
CPC分类号： H03K19/17736 , G11C8/12 , H03K19/1737 , H03K19/17704 , H03K19/17728
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

2. 发明授权

US5963049A Programmable logic array integrated circuit architectures 失效
公开(公告)号：US5963049A
公开(公告)日：1999-10-05
申请号：US807561
申请日：1997-02-28
申请人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
发明人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

3. 发明授权

US5982195A Programmable logic device architectures 失效
标题翻译：可编程逻辑器件架构
公开(公告)号：US5982195A
公开(公告)日：1999-11-09
申请号：US873169
申请日：1997-06-11
申请人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Fung Fung Lee , Cameron McClintock , David W. Mendel , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
发明人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Fung Fung Lee , Cameron McClintock , David W. Mendel , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
IPC分类号： H03K19/177 , H05K1/00 , H05K1/18
CPC分类号： H03K19/17736 , H03K19/17792 , H05K1/0286 , H05K1/181
摘要： A programmable logic device has regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Horizontal interconnection conductors are associated with each row, and vertical interconnection conductors are associated with each column. Local conductors are interspersed between adjacent pairs of regions in each row for supplying signals to the regions on both sides of the local conductors. Subregions of programmable logic in each region generally have a local output and a global output. The global output is only usable to output to the relatively long-distance horizontal and vertical conductors. The local output is additionally usable as a local feedback and as a local connection to an adjacent region.
摘要翻译：可编程逻辑器件具有以这种区域的交叉行和列的二维阵列设置在器件上的可编程逻辑区域。水平互连导体与每行相关联，并且垂直互连导体与每列相关联。局部导体分散在每一行的相邻区域对之间，用于向局部导体两侧的区域提供信号。每个区域的可编程逻辑子区域通常具有本地输出和全局输出。全局输出仅可用于输出到相对较长距离的水平和垂直导体。本地输出可额外用作本地反馈和作为到相邻区域的本地连接。

4. 发明授权

US06366121B2 Programmable logic array integrated circuit architectures 有权
标题翻译：可编程逻辑阵列集成电路架构
公开(公告)号：US06366121B2
公开(公告)日：2002-04-02
申请号：US09865227
申请日：2001-05-25
申请人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
发明人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
IPC分类号： G06F738
CPC分类号： H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate “lonely register” function in modules of the regions.
摘要翻译：可编程逻辑阵列集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域以交叉行和列的区域的二维阵列布置在器件上。几个区域的输出信号共享一组驱动器，用于将区域输出信号应用于在区域之间传送信号的互连导体。这节省了驱动程序资源，并增加了信号路由的灵活性。可以使用各种方法来配置互连导体，以便节省互连导体资源。逻辑区域可以用于直接驱动特定的输入/输出单元，由此简化到I / O单元的信号路由，并且还可能简化I / O单元的结构（例如，通过允许执行某些I / O单元功能在相关的逻辑区域）。区域输出信号路由灵活性也可以被增强以促进组合逻辑的同时执行和区域模块中的单独的“孤独寄存器”功能。

5. 发明授权

US5909126A Programmable logic array integrated circuit devices with interleaved logic array blocks 失效
标题翻译：具有交错逻辑阵列块的可编程逻辑阵列集成电路器件
公开(公告)号：US5909126A
公开(公告)日：1999-06-01
申请号：US672676
申请日：1996-06-28
申请人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
发明人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
IPC分类号： H03K19/04 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728 , H03K19/17796 , H03K19/04
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.
摘要翻译：可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。本地导体也可用于区域内通信，以及相邻区域之间的通信。辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。

6. 发明授权

US07719311B1 Integrated circuit with improved logic cells 有权
标题翻译：具有改进的逻辑单元的集成电路
公开(公告)号：US07719311B1
公开(公告)日：2010-05-18
申请号：US12469348
申请日：2009-05-20
申请人： Fung Fung Lee , Wen Zhou
发明人： Fung Fung Lee , Wen Zhou
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/17728
摘要： The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.
摘要翻译：本发明提供具有改进的逻辑单元的集成电路。在一个实施例中，提供了具有多个逻辑单元（LC）的集成电路，每个LC包括：具有LUT输出端的查找表; 和第一复用器; 其中，第一多路复用器输入端连接到LC的第一输入端，第二多路复用器输入端连接到LUT输出端，多路复用器输出端连接到LC的第一输出端，以及多路复用器选择端子连接到LC的第二输入端子，以选择出现在第一和第二多路复用器输入端上的哪个信号通过; 其中，通过将一个LC的第一输入端子耦合到另一LC的第一输出端子，形成WLUT链。

7. 发明授权

US07412669B1 Generation of graphical design representation from a design specification data file 有权
标题翻译：从设计规范数据文件生成图形设计表示
公开(公告)号：US07412669B1
公开(公告)日：2008-08-12
申请号：US11483239
申请日：2006-07-06
申请人： Fung Fung Lee , Chukwuweta Chukwudebe
发明人： Fung Fung Lee , Chukwuweta Chukwudebe
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Method and apparatus are described for generating a block diagram of an electronic circuit design. In one embodiment, each instance of a multi-master bus, a bus master of a multi-master bus, a bus slave of a multi-master bus, a memory, a co-processor and an input/output port is are identified. Instances of input/output ports are placed about a perimeter of a first area of the diagram. Each instance of a multi-master bus is placed in a bus area within the first area and each bus master is placed in a master area. The bus slaves of a bus are collected in a group, and the group is placed as a single block in a slave area within the first area. The group of bus slave slaves is aligned with a bus master. A diagrammatic representation is output consistent with the placement representations.
摘要翻译：描述了用于生成电子电路设计的框图的方法和装置。在一个实施例中，识别多主母线，多主总线的总线主机，多主总线的总线从机，存储器，协处理器和输入/输出端口的每个实例。输入/输出端口的实例围绕图的第一个区域的周边放置。多主总线的每个实例被放置在第一区域内的总线区域中，并且每个总线主机被放置在主区域中。总线的总线从站被收集在一组中，并且组被作为单个块放置在第一区域内的从属区域中。总线从站的组与总线主站对齐。输出与放置表示一致的图示表示。

8. 发明授权

US5844854A Programmable logic device with two dimensional memory addressing 失效
标题翻译：具有二维存储器寻址的可编程逻辑器件
公开(公告)号：US5844854A
公开(公告)日：1998-12-01
申请号：US759304
申请日：1996-12-02
申请人： Fung Fung Lee
发明人： Fung Fung Lee
IPC分类号： G11C8/00 , G11C8/12 , H03K19/177 , G11C13/00
CPC分类号： H03K19/1776 , G11C8/00 , G11C8/12
摘要： A programmable logic array integrated circuit device having a memory array in which data can be accessed in either a transposed or nontransposed mode. The memory array has multiple rows and columns of memory cells. Each row of cells can be viewed as a matrix made up of virtual rows and virtual columns. Data in a given row of the memory array can be accessed using nontransposed data words that contain data bits corresponding to cells in the virtual rows. Data in the given row can also be accessed using transposed data words that contain data bits corresponding to cells in the virtual columns.
摘要翻译：一种具有存储器阵列的可编程逻辑阵列集成电路器件，其中数据可以以转置或非转置模式访问。存储器阵列具有多个存储单元的行和列。每行单元格可以被视为由虚拟行和虚拟列组成的矩阵。可以使用包含对应于虚拟行中的单元的数据位的非转置数据字来访问存储器阵列的给定行中的数据。也可以使用包含与虚拟列中的单元格对应的数据位的转置数据字来访问给定行中的数据。

9. 发明授权

US5672985A Programmable logic array integrated circuits with carry and/or cascade rings 失效
标题翻译：具有进位和/或级联环的可编程逻辑阵列集成电路
公开(公告)号：US5672985A
公开(公告)日：1997-09-30
申请号：US574351
申请日：1995-12-18
申请人： Fung Fung Lee
发明人： Fung Fung Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704
摘要： Logic regions in a programmable logic array integrated circuit are interconnected in a closed loop or ring by carry and/or cascade connections. Because such a loop or ring has no ends, a user's logic that uses carry or cascade connections can be placed anywhere along the ring. This eliminates a prior art constraint on the placement of a user's logic on the integrated circuit.
摘要翻译：可编程逻辑阵列集成电路中的逻辑区域通过进位和/或级联连接在闭环或环中互连。因为这样的环或环没有结束，所以使用进位或级联连接的用户逻辑可以放置在环上的任何地方。这消除了在集成电路上放置用户逻辑的现有技术约束。

10. 发明授权

US07915917B2 Integrated circuit with improved logic cells 有权
公开(公告)号：US07915917B2
公开(公告)日：2011-03-29
申请号：US12753623
申请日：2010-04-02
申请人： Fung Fung Lee , Wen Zhou
发明人： Fung Fung Lee , Wen Zhou
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17728
摘要： The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.

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