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    • 1. 发明授权
      US5796149A Semiconductor memory using different concentration impurity diffused layers 失效
    • Semiconductor memory using different concentration impurity diffused layers
    • 半导体存储器采用不同浓度的杂质扩散层
    • US5796149A
    • 1998-08-18
    • US524672
    • 1995-09-08
    • Fumitaka Sugaya , Yasuo Sato
    • Fumitaka Sugaya , Yasuo Sato
    • H01L21/8246 , H01L29/78 , H01L29/76 , H01L29/94
    • H01L27/11266 , H01L29/7835
    • A semiconductor memory which includes first and second memory cells, wherein the first memory cells include first MOS transistors each having impurity diffused layers provided inside of both of a source and a drain to expanding source and drain regions, the second memory cells include second or third MOS transistors each having an impurity diffused layer provided inside of one of a source and a drain or include fourth MOS transistors each having no impurity diffused layer provided inside of either thereof, as well as a method for fabricating the semiconductor memory. Differences in threshold voltage between the first and second to fourth MOS transistors are utilized as differences in storage status between the first and second memory cells so that data "0" or "1" is stored in each memory cell. There are also provided a semiconductor memory wherein differences between the first to fourth MOS transistors in the drain-source current flowing through the transistors when subjected to application of an identical gate voltage thereto are utilized to store four sorts of data in one memory cell, and provided a method for fabricating the semiconductor memory.
    • 一种半导体存储器，包括第一和第二存储单元，其中第一存储单元包括第一MOS晶体管，每个第一MOS晶体管具有设置在源极和漏极两者内部的扩散源极和漏极区的杂质扩散层，第二存储单元包括第二或第三 每个具有设置在源极和漏极之一内部的杂质扩散层的MOS晶体管或包括设置在其任一内侧的不具有杂质扩散层的第四MOS晶体管以及半导体存储器的制造方法。 利用第一和第二至第四MOS晶体管之间的阈值电压的差异作为第一和第二存储单元之间的存储状态的差异，从而在每个存储单元中存储数据“0”或“1”。 还提供了一种半导体存储器，其中利用在施加相同的栅极电压时流过晶体管的漏 - 源电流中的第一至第四MOS晶体管之间的差异来将四种数据存储在一个存储单元中，以及 提供了一种用于制造半导体存储器的方法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US06232182B1 Non-volatile semiconductor memory device including memory transistor with a composite gate structure and method of manufacturing the same 失效
    • Non-volatile semiconductor memory device including memory transistor with a composite gate structure and method of manufacturing the same
    • 包括具有复合栅极结构的存储晶体管及其制造方法的非易失性半导体存储器件
    • US06232182B1
    • 2001-05-15
    • US09070754
    • 1998-05-01
    • Fumitaka Sugaya
    • Fumitaka Sugaya
    • H01L21336
    • H01L27/11521 , H01L21/28194 , H01L27/115 , H01L27/11524 , H01L29/42324 , H01L29/511
    • A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region with a first insulating film interposed therebetween and including a laminate of a floating gate electrode, a second insulating film and a control gate electrode; a gate electrode of the selection transistor formed on the surface of the semiconductor substrate at its second region close to the first region with a third insulating film interposed therebetween; and an impurity diffusion layer formed in the semiconductor substrate at its region between the first and second regions and functioning as a drain of the memory transistor, common to a source of the selection transistor, the impurity diffusion layer having at least an extension region extending to a part of the semiconductor substrate disposed under the composite gate structure, the extension region having first, second and third layers wherein the first and second layers include first and second impurities at first and second different concentrations, respectively, and the third layer includes a third impurity at a third concentration higher than any one of the first and second concentrations and a method of manufacturing the non-volatile semiconductor memory device as above-mentioned.
    • 一种包括具有存储晶体管和选择晶体管的存储单元的非易失性半导体存储器件，包括：存储晶体管的复合栅极结构，其在其第一区域的半导体衬底的表面上形成有介于其间的第一绝缘膜， 包括浮栅电极，第二绝缘膜和控制栅电极的层压体; 所述选择晶体管的栅极形成在所述半导体衬底的表面上，在靠近所述第一区域的第二区域处具有介于其间的第三绝缘膜; 以及杂质扩散层，其形成在半导体衬底中的位于第一和第二区域之间的区域中，并且作为选择晶体管的源极共用的存储晶体管的漏极，杂质扩散层至少具有延伸到 所述半导体衬底的设置在所述复合栅极结构下方的部分，所述延伸区域具有第一，第二和第三层，其中所述第一和第二层分别包括第一和第二不同浓度的第一和第二杂质，并且所述第三层包括第三层 第三浓度高于第一和第二浓度中的任何一种的杂质，以及制造如上所述的非易失性半导体存储器件的方法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5780893A Non-volatile semiconductor memory device including memory transistor with a composite gate structure 失效
    • Non-volatile semiconductor memory device including memory transistor with a composite gate structure
    • 包括具有复合栅极结构的存储晶体管的非易失性半导体存储器件
    • US5780893A
    • 1998-07-14
    • US769351
    • 1996-12-19
    • Fumitaka Sugaya
    • Fumitaka Sugaya
    • H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/76 , H01L29/788
    • H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324 , H01L29/511 , H01L21/28194
    • A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region with a first insulating film interposed therebetween and including a laminate of a floating gate electrode, a second insulating film and a control gate electrode; a gate electrode of the selection transistor formed on the surface of the semiconductor substrate at its second region close to the first region with a third insulating film interposed therebetween; and an impurity diffusion layer formed in the semiconductor substrate at its region between the first and second regions and functioning as a drain of the memory transistor, common to a source of the selection transistor, the impurity diffusion layer having at least an extension region extending to a part of the semiconductor substrate disposed under the composite gate structure, the extension region having first, second and third layers wherein the first and second layers include first and second impurities at first and second different concentrations, respectively, and the third layer includes a third impurity at a third concentration higher than any one of the first and second concentrations and a method of manufacturing the non-volatile semiconductor memory device as above-mentioned.
    • 一种包括具有存储晶体管和选择晶体管的存储单元的非易失性半导体存储器件，包括：存储晶体管的复合栅极结构，其在其第一区域的半导体衬底的表面上形成有介于其间的第一绝缘膜， 包括浮栅电极，第二绝缘膜和控制栅电极的层压体; 所述选择晶体管的栅极形成在所述半导体衬底的表面上，在靠近所述第一区域的第二区域处具有介于其间的第三绝缘膜; 以及杂质扩散层，其形成在半导体衬底中的位于第一和第二区域之间的区域中，并且作为选择晶体管的源极共用的存储晶体管的漏极，杂质扩散层至少具有延伸到 所述半导体衬底的设置在所述复合栅极结构下方的部分，所述延伸区域具有第一，第二和第三层，其中所述第一和第二层分别包括第一和第二不同浓度的第一和第二杂质，并且所述第三层包括第三层 第三浓度高于第一和第二浓度中的任何一种的杂质，以及制造如上所述的非易失性半导体存储器件的方法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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