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1. 发明授权

US4905051A Fixing means for electrophotographic copier 失效
标题翻译：电子照相复印机的固定装置
公开(公告)号：US4905051A
公开(公告)日：1990-02-27
申请号：US249231
申请日：1988-09-23
申请人： Fumio Satoh , Yoichi Shimazawa , Yasuhiro Takai , Katsumi Nakanishi
发明人： Fumio Satoh , Yoichi Shimazawa , Yasuhiro Takai , Katsumi Nakanishi
IPC分类号： G03G15/20
CPC分类号： G03G15/2042 , G03G15/2039
摘要： A fixing means for an electrophotographic copier includes a first roller and a second roller which are compressed against each other and serve to fix toner images on an image transferring medium passed therebetween. A control means is programmed to operate the rollers such that the heating of the second roller is continued for a predetermined length of time or until the surface temperature of the second roller reaches a certain predetermined temperature level after the surface temperature of the first roller reaches another predetermined temperature level such that the second roller is prevented from cooling down suddenly after the fixing operation is started. In another aspect of the present invention, the size of the image transferring medium passed between the rollers is detected and the heaters for the rollers are controlled accordingly such that temperature variations on the roller surfaces can be reduced and hence the roller lifetimes can be improved.
摘要翻译：电子照相复印机的固定装置包括彼此压缩的第一辊和第二辊，并用于将调色剂图像定影在通过它们的图像转印介质上。控制装置被编程为操作辊，使得第二辊的加热持续预定的时间长度，或者直到第一辊的表面温度达到另一辊之后第二辊的表面温度达到一定的预定温度水平预定的温度水平，使得在定影操作开始之后防止第二辊突然冷却。在本发明的另一方面，检测到在辊之间通过的图像转印介质的尺寸，并且相应地控制用于辊的加热器，使得辊表面上的温度变化可以减小，因此可以提高辊的使用寿命。

2. 发明授权

US5041878A Method for forming and transferring color images 失效
标题翻译：彩色图像的形成和传送方法
公开(公告)号：US5041878A
公开(公告)日：1991-08-20
申请号：US456864
申请日：1989-12-27
申请人： Yasuhiro Takai , Taisuke Kamimura , Yoichi Shimazawa , Etsuzi Nukushina
发明人： Yasuhiro Takai , Taisuke Kamimura , Yoichi Shimazawa , Etsuzi Nukushina
IPC分类号： G03G15/01 , G03G15/16
CPC分类号： G03G15/0131 , G03G15/1605
摘要： In a transfer method of a colored image, the process speed is initially properly set in accordance with the size of a copy paper sheet to be used. The transfer voltage is then changed in accordance with the process speed. After these processes, a colored toner image formed on a photoconductor is first transferred onto an intermediate transfer medium and then further transferred onto the copy paper sheet.
摘要翻译：在彩色图像的转印方法中，根据要使用的复印纸的尺寸，初始地适当地设定处理速度。然后根据处理速度改变转印电压。在这些处理之后，形成在光电导体上的着色调色剂图像首先转印到中间转印介质上，然后进一步转印到复印纸上。

3. 发明授权

US5040028A Image forming apparatus with a toner transfer device 失效
标题翻译：具有调色剂转印装置的图像形成装置
公开(公告)号：US5040028A
公开(公告)日：1991-08-13
申请号：US478823
申请日：1990-02-12
申请人： Taisuke Kamimura , Yasuhiro Takai , Yoichi Shimazawa , Etsuji Nukushina , Hideo Matsuda
发明人： Taisuke Kamimura , Yasuhiro Takai , Yoichi Shimazawa , Etsuji Nukushina , Hideo Matsuda
IPC分类号： G03G15/16
CPC分类号： G03G15/1605
摘要： A toner transfer device which transfers toner on a photoconductor to an intermediate transfer belt applied on a plurality of rollers, wherein at least part of the surface of the photoconductor moves in an arc while being pressed against the intermediate transfer belt, the toner transfer device comprising: a pair of transfer rollers disposed along the intermediate transfer belt between two of the rollers in such a manner that the part of the surface of the photoconductor which moves in an arc is positioned between the transfer rollers, at least part of each transfer roller being located outside each of two tangents, one of the tangents touching the photoconductor and one of the two rollers, the other tangent touching the photoconductor and the other roller, thereby allowing a certain length of the intermediate transfer belt between the two transfer rollers to be pressed against the part of the surface of the photoconductor moving in an arc; and a means for applying voltage to the transfer rollers, the voltage polarity being opposite to that of the toner.
摘要翻译：一种调色剂转印装置，其将感光体上的调色剂转印到施加在多个辊上的中间转印带上，其中所述感光体的表面的至少一部分在被压靠在所述中间转印带上的同时移动，所述调色剂转印装置包括：沿着中间转印带设置在两个辊之间的一对转印辊，使得以电弧方式移动的感光体的表面的一部分位于转印辊之间，每个转印辊的至少一部分为位于两个切线的每一个外侧，其中一个切线触摸感光体和两个辊之一，另一个切线接触光电导体和另一个辊，从而允许两个转印辊之间的一定长度的中间转印带被压制抵抗光电导体表面的弧形运动; 以及用于向转印辊施加电压的装置，其电压极性与调色剂的极性相反。

4. 发明授权

US07944262B2 Duty correction circuit 有权
标题翻译：负责校正电路
公开(公告)号：US07944262B2
公开(公告)日：2011-05-17
申请号：US12453652
申请日：2009-05-18
申请人： Koji Kuroki , Yasuhiro Takai
发明人： Koji Kuroki , Yasuhiro Takai
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.
摘要翻译：使用至少一个延迟电路形成占空比校正电路，所述至少一个延迟电路由包括三个不同导电类型的晶体管的第一反相器和包括不同导通类型的三个其它晶体管的第二反相器组成，并且其延迟并调整在前沿/后沿定时，以便基于由检测输出时钟信号的占空比的偏置电路产生的第一或第二偏置电压将其转换为输出时钟信号。占空比校正电路基于第一偏置电压降低具有高占空比的输出时钟信号的高电平周期。或者，占空比校正电路基于第二偏置电压增加具有低占空比的输出时钟信号的高电平周期。

5. 发明授权

US07772911B2 Timing control circuit and semiconductor storage device 有权
标题翻译：定时控制电路和半导体存储设备
公开(公告)号：US07772911B2
公开(公告)日：2010-08-10
申请号：US12208978
申请日：2008-09-11
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： G06F1/04
CPC分类号： H03K5/135 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C19/00
摘要： Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal.
摘要翻译：公开了一种定时控制电路，其接收具有周期T1的第一时钟，以相等间隔彼此间隔开的L个不同相位的一组第二时钟，以及提供给其的选择信号m，n，并产生从第一时钟信号的上升沿大约为td = m·T1 + n·（T2 / L）的延迟td。定时控制电路包括粗延迟电路和精细延迟电路。粗略延迟电路包括用于在激活信号被激活之后对第一时钟信号的上升沿进行计数的计数器，并产生其第一时钟信号的延迟量大约为m·T1的粗略定时信号。精细延迟电路包括L个并联设置的多相时钟控制延迟电路，通过n·T2 / L延迟由L组第二时钟组的相应时钟对粗略定时信号进行采样的定时，或者产生延迟脉冲，从而产生精细定时信号。

6. 发明授权

US07734243B2 Image forming apparatus 有权
标题翻译：图像形成装置
公开(公告)号：US07734243B2
公开(公告)日：2010-06-08
申请号：US11336901
申请日：2006-01-23
申请人： Toshiki Takiguchi , Kouji Wakamoto , Tatsuya Inoue , Yasuhiro Takai
发明人： Toshiki Takiguchi , Kouji Wakamoto , Tatsuya Inoue , Yasuhiro Takai
IPC分类号： G03G15/00
CPC分类号： G03G15/5008
摘要： In an image forming apparatus of the present invention, an idle roller once stops rotating when a front edge of a sheet conveyed reaches the idle roller. The idle roller restarts rotating at such a timing that a front edge of a toner image on a photoreceptor and a front edge of an image writing position on the sheet are aligned with each other. Then, even if a rear edge of the sheet is still in the idle roller, the idle roller stops rotating when the front edge of the sheet is sandwiched between a transfer roller and the photoreceptor. By carrying out such operations, it is possible to avoid by a very simple way an occurrence of a slip phenomenon that is a phenomenon of slipping of the sheet with respect to the photoreceptor while suppressing a reduction in image quality as much as possible. In addition, it is also possible to surely secure a blank space formed at a rear edge portion of the sheet.
摘要翻译：在本发明的图像形成装置中，当传送的纸张的前缘到达空转辊时，空转辊一次停止旋转。空转辊重新开始旋转，使得感光体上的调色剂图像的前边缘和片材上的图像书写位置的前边缘彼此对准。然后，即使片材的后边缘仍然在空转辊中，当片材的前边缘夹在转印辊和感光体之间时，空转辊停止旋转。通过进行这种操作，可以通过非常简单的方式避免出现作为尽可能多地抑制图像质量降低的片材相对于感光体的现象的滑动现象。此外，还可以确保形成在片材的后边缘部分处的空白空间。

7. 发明授权

US07688655B2 Semiconductor memory device and test method therefor 失效
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US07688655B2
公开(公告)日：2010-03-30
申请号：US11747552
申请日：2007-05-11
申请人： Yasuhiro Takai
发明人： Yasuhiro Takai
IPC分类号： G11C29/00
CPC分类号： G11C29/50016 , G11C11/401 , G11C11/406 , G11C11/40622 , G11C29/14
摘要： Disclosed is a semiconductor memory device, in which the refresh period of a fail cell or cells is set so as to be shorter than that of the normal cells, comprises a control circuit for exercising control in such a manner that, if, when refreshing the cell of a first address, generated responsive to a refresh command, with an input control signal being of a first value, a second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the information ore-programmed in a refresh redundant ROM, the cell of the second address is refreshed, and also in such a manner that, if, with the input control signal of a second value, the second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the predetermined information, only the cell of the second address is refreshed, without refreshing the cell of the first address, generated responsive to the refresh command.
摘要翻译：公开了一种半导体存储器件，其中将故障单元或单元的刷新周期设置为短于正常单元的刷新周期，包括用于以这样的方式进行控制的控制电路，即如果在刷新被确定为响应于刷新命令产生的第一地址的单元，其中输入控制信号是第一值，对于来自第一地址的预定位不同的第二地址被确定为对应于故障单元基于在刷新冗余ROM中编程的信息，第二地址的单元被刷新，并且还以这样的方式，如果利用第二值的输入控制信号，第二地址不同于来自第一地址的预定比特的值被确定为对应于故障小区，基于预定信息，仅刷新第二地址的小区，而不刷新第一地址的小区，生成的响应刷新命令。

8. 发明申请

US20090289676A1 DLL circuit 有权
标题翻译： DLL电路
公开(公告)号：US20090289676A1
公开(公告)日：2009-11-26
申请号：US12453764
申请日：2009-05-21
申请人： Yasuhiro Takai
发明人： Yasuhiro Takai
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03L7/0814 , H03K5/13 , H03K5/133 , H03K2005/00052 , H03L7/0818
摘要： A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an interpolation circuit. The coarse delay adjustment circuit delays a reference clock signal by a plurality of delay stages so as to provide the first fine delay circuit with two phase signals having the phase difference of two delay stages, which are then converted into two delay signals having the phase difference of one delay stage. The delay signals are subjected to interpolation, thus producing an output clock signal. Due to a reduction of the phase difference in the first fine delay circuit, it is possible to reduce the minimum operation cycle of the interpolation circuit and to thereby increase the maximum operation frequency of the DLL circuit.
摘要翻译： DLL电路包括粗延迟调整电路和精细延迟调整电路，其还包括作为内插电路的第一精细延迟电路和第二精细延迟电路。粗延迟调整电路通过多个延迟级对参考时钟信号进行延时，以向第一精细延迟电路提供具有两个延迟级的相位差的两个相位信号，然后将其转换成具有相位差的两个延迟信号一个延迟阶段。对延迟信号进行内插，从而产生输出时钟信号。由于第一精细延迟电路中的相位差减小，可以减小内插电路的最小工作周期，从而增加DLL电路的最大工作频率。

9. 发明授权

US07597323B2 Paper feeder and image forming apparatus 有权
标题翻译：送纸器和成像设备
公开(公告)号：US07597323B2
公开(公告)日：2009-10-06
申请号：US11878455
申请日：2007-07-24
申请人： Tadasu Taniguchi , Norichika Katsura , Masahiko Fujita , Yasunobu Ohkawa , Masaya Asakawa , Yasuhiro Takai
发明人： Tadasu Taniguchi , Norichika Katsura , Masahiko Fujita , Yasunobu Ohkawa , Masaya Asakawa , Yasuhiro Takai
IPC分类号： B65H5/02
CPC分类号： B65H5/062 , B65H2402/352 , B65H2404/1431 , B65H2511/13 , B65H2515/34 , B65H2220/01 , B65H2220/02 , B65H2220/04
摘要： A paper feeder comprises an acquiring device, a driving roller, driven rollers, a driven roller supporter, a driver, and a controller. The acquiring device acquires thickness information on a sheet of paper. The driving roller rotates by being supplied with torque. The driven rollers rotate with the driving roller when in compressive contact with the driving roller. The driven roller supporter so supports the driven rollers that each of them can rotate under a different rotational load. The driver changes the position of the driven roller supporter relative to the driving roller. The controller selects one of the driven rollers on the basis of the thickness information and so activates the driver as to bring the selected roller into compressive contact with the driving roller.
摘要翻译：送纸器包括采集装置，驱动辊，从动辊，从动辊支架，驱动器和控制器。获取装置获取一张纸上的厚度信息。驱动辊通过转矩旋转。当与驱动辊压接时，从动辊与驱动辊一起旋转。从动辊支撑器支撑从动辊，它们中的每一个可以在不同的旋转负载下旋转。驱动器改变从动辊支架相对于驱动辊的位置。控制器基于厚度信息来选择一个从动辊，从而激活驱动器以使所选择的辊与驱动辊压接。

10. 发明申请

US20090146716A1 Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
标题翻译：定时控制电路，定时生成系统，定时控制方法和半导体存储器件
公开(公告)号：US20090146716A1
公开(公告)日：2009-06-11
申请号：US12314207
申请日：2008-12-05
申请人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
发明人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
IPC分类号： H03H11/26
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
摘要翻译：定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟延迟元件定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。定时信号延迟的变化减小。

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