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    • 7. 发明授权
    • Information processing system, information compression device, information decompression device, information processing method, and program
    • 信息处理系统,信息压缩装置,信息解压装置,信息处理方法和程序
    • US09553604B2
    • 2017-01-24
    • US13262181
    • 2010-03-19
    • Hiroaki Inoue
    • Hiroaki Inoue
    • H03M7/30G11C7/10H04L29/12G11C29/00
    • H03M7/30G11C7/103G11C29/003H04L29/12311
    • In order to improve the compression rate for configuration information including address information and data information when transmitting or storing configuration information which includes addresses and data having differing characteristics, an information compression device is provided with a compressor which receives as input and compresses the configuration information provided with the addresses and data, and a compressed information storage module for storing the configuration information which is compressed, that is, compressed configuration information, as the information to be decompressed for the user, said compressor including an information separating module for separating the configuration information into address information and data information, an address compressor and data compressor which separately compress the separated address information and data information, and a compressed information outputting module for combining the compressed address information and data information and outputting the result as compressed configuration information.
    • 为了在发送或存储具有不同特征的地址和数据的配置信息的情况下提高包括地址信息和数据信息的配置信息的压缩率,信息压缩装置设置有作为输入接收并压缩提供的配置信息的压缩器 具有地址和数据的压缩信息存储模块,以及用于将被压缩的配置信息(即,压缩配置信息)存储为要为用户解压缩的信息的压缩信息存储模块,所述压缩器包括用于分离配置信息的信息分离模块 地址信息和数据信息,分离地压缩分离的地址信息和数据信息的地址压缩器和数据压缩器,以及压缩信息输出模块,用于将压缩的地址信息和数据 信息并将结果作为压缩配置信息输出。
    • 8. 发明授权
    • Semiconductor integrated circuit device, method of controlling semiconductor integrated circuit device, and cache device
    • 半导体集成电路器件,半导体集成电路器件的控制方法及缓存器件
    • US09164905B2
    • 2015-10-20
    • US13393814
    • 2010-08-18
    • Hiroaki Inoue
    • Hiroaki Inoue
    • G06F12/00G06F12/08
    • G06F12/0802G06F2212/1028Y02D10/13
    • There are provided a semiconductor integrated circuit device, a method of controlling a semiconductor integrated circuit device, and a cache device capable of efficiently implementing power saving, wherein the cache device includes a low-voltage operation enabling cache (200), and a small-area cache (300) having a type different from that of the cache (200), the cache (200) and the cache (300) being independently supplied with source voltage; the cache (200) being operable at a voltage lower than the lower limit voltage at which the cache (300) is operable; a cache control unit (400) operating switchable controls between a first mode allowing only the cache (200) to operate, and a second mode allowing the cache (200) or the cache (300) to operate; and the cache (200) in the first mode operating to supply a voltage below the lower limit voltage at which the cache (300) is operable, while interrupting power supply to the cache (300).
    • 提供了一种半导体集成电路器件,一种半导体集成电路器件的控制方法和能够有效地实现功率节省的高速缓存器件,其中该高速缓存器件包括一个使能高速缓存(200)的低压工作, 区域缓存(300)具有与高速缓存(200)不同的类型,高速缓存(200)和高速缓存(300)被独立地提供源电压; 高速缓存(200)可操作在低于高速缓存(300)可操作的下限电压的电压; 高速缓存控制单元(400)在允许仅高速缓存(200)操作的第一模式和允许高速缓存(200)或高速缓存(300)操作的第二模式之间操作可切换控制; 以及在所述第一模式下的所述高速缓存(200)工作以提供低于所述高速缓存(300)可操作的所述下限电压的电压,同时中断向所述高速缓存(300)的电力供应。