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1. 发明授权

US06243732B1 Data processor and data processing system 有权
标题翻译：数据处理器和数据处理系统
公开(公告)号：US06243732B1
公开(公告)日：2001-06-05
申请号：US09479075
申请日：2000-01-07
申请人： Fumio Arakawa , Norio Nakagawa , Tetsuya Yamada , Yonetaro Totsuka
发明人： Fumio Arakawa , Norio Nakagawa , Tetsuya Yamada , Yonetaro Totsuka
IPC分类号： G06F732
CPC分类号： G06F7/509 , G06F7/483 , G06F7/5443 , G06F7/548 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.
摘要翻译：数据处理器包括并入浮点单元中的算术部分，其中运算部分包括多个乘法器，从分别不同的数据输入信号线组提供浮点数的尾数部分，并执行所提供的尾数部分的相乘;对准器接收相应乘法器的输出并执行对准移位，指数处理部分，用于基于产生浮点数的指数部分，产生对准器的对准偏移量和归一化前的指数，多输入加法器和指数在正常化之前，以高速和高精度降低电路的尺寸并且以浮点数进行内部产品操作等。

2. 发明授权

US6038582A Data processor and data processing system 失效
标题翻译：数据处理器和数据处理系统
公开(公告)号：US6038582A
公开(公告)日：2000-03-14
申请号：US950664
申请日：1997-10-15
申请人： Fumio Arakawa , Norio Nakagawa , Tetsuya Yamada , Yonetaro Totsuka
发明人： Fumio Arakawa , Norio Nakagawa , Tetsuya Yamada , Yonetaro Totsuka
IPC分类号： G06F7/38 , G06F7/487 , G06F7/50 , G06F7/509 , G06F7/53 , G06F7/544 , G06F7/548 , G06F9/30 , G06F9/302 , G06F9/38 , G06F17/10 , G06T1/20 , G06F7/42
CPC分类号： G06F7/509 , G06F7/5443 , G06F7/548 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F7/483
摘要： A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.
摘要翻译：数据处理器包括并入浮点单元中的算术部分，其中运算部分包括多个乘法器，从分别不同的数据输入信号线组提供浮点数的尾数部分，并执行所提供的尾数部分的相乘;对准器接收相应乘法器的输出并执行对准移位，指数处理部分，用于基于产生浮点数的指数部分，产生对准器的对准偏移量和归一化前的指数，多输入加法器和指数在正常化之前，以高速和高精度降低电路的尺寸并且以浮点数进行内部产品操作等。

3. 发明授权

US06327605B2 Data processor and data processing system 有权
公开(公告)号：US06327605B2
公开(公告)日：2001-12-04
申请号：US09810485
申请日：2001-03-19
申请人： Fumio Arakawa , Norio Nakagawa , Tetsuya Yamada , Yonetaro Totsuka
发明人： Fumio Arakawa , Norio Nakagawa , Tetsuya Yamada , Yonetaro Totsuka
IPC分类号： G06F738
CPC分类号： G06F7/509 , G06F7/483 , G06F7/5443 , G06F7/548 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.

4. 发明申请

US20090113186A1 MICROCONTROLLER AND CONTROLLING SYSTEM 审中-公开
标题翻译：微控制器和控制系统
公开(公告)号：US20090113186A1
公开(公告)日：2009-04-30
申请号：US12262173
申请日：2008-10-30
申请人： Naoki KATO , Tetsuya Yamada , Fumio Arakawa , Hiromichi Yamada , Shigeru Oho , Makoto Ishikawa
发明人： Naoki KATO , Tetsuya Yamada , Fumio Arakawa , Hiromichi Yamada , Shigeru Oho , Makoto Ishikawa
IPC分类号： G06F9/22 , G06F7/42 , G06F3/00
CPC分类号： G06F9/30025 , G06F7/483 , G06F9/3001 , H03M7/24
摘要： A microcontroller and a controlling system having the same are provided, in which the increase in the program code for performing floating-point arithmetic, in particular, the increase in the amount of code due to a variable are suppressed, and the processing overhead for converting fixed-point data into floating-point data is reduced. The microcontroller includes a floating-point converter which inputs integer data and corresponding decimal point position data as fixed-point data and which converts the input data into floating-point data by acquiring a fraction part, an exponent part, and a sign of the floating type from the input data, and a floating-point arithmetic logic unit which receives the output of the floating-point converter and calculates the floating-point data. The floating-point converter acquires the exponent part by performing addition and subtraction of the decimal point position data and the shift amount of the fraction part to the integer data.
摘要翻译：提供了一种微控制器及其控制系统，其中用于执行浮点运算的程序代码的增加，特别是由于变量引起的代码量的增加被抑制，并且用于转换的处理开销定点数据进入浮点数据减少。微控制器包括一个浮点转换器，它将整数数据和对应的小数点位置数据作为定点数据输入，并通过获取浮点数的分数部分，指数部分和符号将输入数据转换为浮点数据从输入数据输入;以及浮点算术逻辑单元，接收浮点转换器的输出并计算浮点数据。浮点转换器通过对小数点位置数据和分数部分的移位量进行加，减来获取指数部分到整数数据。

5. 发明授权

US08341204B2 Vector SIMD processor 有权
标题翻译：矢量SIMD处理器
公开(公告)号：US08341204B2
公开(公告)日：2012-12-25
申请号：US12497208
申请日：2009-07-02
申请人： Fumio Arakawa , Tetsuya Yamada
发明人： Fumio Arakawa , Tetsuya Yamada
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F7/483 , G06F7/5443 , G06F9/3877 , G06F9/3887 , G06F15/8023 , G06F15/8092
摘要： A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining the efficiency of the floating-point length-4 vector inner product execution units is to be implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.
摘要翻译：通过构成与单指令多数据（SIMD）兼容的浮点内部产品执行单元，从而提高操作处理能力，可以提高其操作并行性水平的数据处理器。要实现一个可以显着提高每个指令的运行并行性水平，同时保持浮点长度为4的矢量内积执行单元的效率的操作系统。即使在广泛的操作系统可用的情况下，浮点长度-4向量内积执行单元也以最小宽度（单精度为32位）定义，并组成内部产品执行单元与SIMD兼容。内部产品执行单元和SIMD兼容组合的相互增强效应显着提高了操作并行性的水平。组合浮点长度-4向量内积执行单元，以计算长度为4的向量的内积和与SIMD并行的标量并行的标量之和，得到每周期32 FLOPS的处理能力。

6. 发明授权

US07567996B2 Vector SIMD processor 有权
标题翻译：矢量SIMD处理器
公开(公告)号：US07567996B2
公开(公告)日：2009-07-28
申请号：US11212736
申请日：2005-08-29
申请人： Fumio Arakawa , Tetsuya Yamada
发明人： Fumio Arakawa , Tetsuya Yamada
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F7/483 , G06F7/5443 , G06F9/3877 , G06F9/3887 , G06F15/8023 , G06F15/8092
摘要： A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining the efficiency of the floating-point length-4 vector inner product execution units is to be implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.
摘要翻译：通过构成与单指令多数据（SIMD）兼容的浮点内部产品执行单元，从而提高操作处理能力，可以提高其操作并行性水平的数据处理器。要实现一个可以显着提高每个指令的运行并行性水平，同时保持浮点长度为4的矢量内积执行单元的效率的操作系统。即使在广泛的操作系统可用的情况下，浮点长度-4向量内积执行单元也以最小宽度（单精度为32位）定义，并组成内部产品执行单元与SIMD兼容。内部产品执行单元和SIMD兼容组合的相互增强效应显着提高了操作并行性的水平。组合浮点长度-4向量内积执行单元，以计算长度为4的向量的内积和与SIMD并行的标量并行的标量之和，得到每周期32 FLOPS的处理能力。

7. 发明授权

US07243119B1 Floating point computing unit 有权
标题翻译：浮点计算单元
公开(公告)号：US07243119B1
公开(公告)日：2007-07-10
申请号：US10362775
申请日：2000-09-26
申请人： Tetsuya Yamada , Motonobu Tonomura , Fumio Arakawa
发明人： Tetsuya Yamada , Motonobu Tonomura , Fumio Arakawa
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F7/483 , G06F7/4873 , G06F7/5375 , G06F7/5525 , G06F2207/382 , G06F2207/5528
摘要： A Sweeney Robertson Tocher (SRT) divider and a square root extractor of floating point double-precision bit width, including a selector of single-precision and double-precision, a carry propagation adder (CPA) for conducting carry propagation of a partial remainder, a quotient digit selector circuit for making selection on a quotient digit, and a selector of a divisor or a partial square root extractor circuit, in a lower side thereof. A selector for selecting the propagation of carry between a carry save adder (CSA) in the upper side and the lower side thereof is provided, and a selector of a starting position within a quotient production circuit is provided, thereby enabling the execution of two (2) calculations, such as, division or square root extraction of the floating point single-precision, at the same time, but without increasing the bit width of a computing unit. Also, with the square root extraction, it is possible to execute two (2) calculations of single-precision in parallel, in a similar manner, by adding a partial square root extraction circuit thereinto.
摘要翻译：一个Sweeney Robertson Tocher（SRT）分频器和一个浮点双精度位宽的平方根提取器，包括单精度和双精度的选择器，用于进行部分余数的进位传播的进位传播加法器（CPA）用于在商数上进行选择的商数选择器电路，以及在其下侧的除数或部分平方根提取器电路的选择器。提供了用于选择在上侧的进位存储加法器（CSA）和其下侧之间的进位传播的选择器，并且提供了在商生产电路内的起始位置的选择器，从而使得能够执行两个 2）计算，如分割或平方根提取浮点单精度，同时，但不增加计算单元的位宽。此外，通过平方根提取，可以以类似的方式通过将部分平方根提取电路加到其中来并行地执行单精度的两（2）次计算。

8. 发明授权

US07028066B2 Vector SIMD processor 有权
公开(公告)号：US07028066B2
公开(公告)日：2006-04-11
申请号：US09800507
申请日：2001-03-08
申请人： Fumio Arakawa , Tetsuya Yamada
发明人： Fumio Arakawa , Tetsuya Yamada
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F7/483 , G06F7/5443 , G06F9/3877 , G06F9/3887 , G06F15/8023 , G06F15/8092
摘要： A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining the efficiency of the floating-point length-4 vector inner product execution units is to be implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.

9. 发明申请

US20090271591A1 VECTOR SIMD PROCESSOR 有权
标题翻译：矢量SIMD处理器
公开(公告)号：US20090271591A1
公开(公告)日：2009-10-29
申请号：US12497208
申请日：2009-07-02
申请人： Fumio ARAKAWA , Tetsuya Yamada
发明人： Fumio ARAKAWA , Tetsuya Yamada
IPC分类号： G06F15/76 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3885 , G06F7/483 , G06F7/5443 , G06F9/3877 , G06F9/3887 , G06F15/8023 , G06F15/8092
摘要： A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining the efficiency of the floating-point length-4 vector inner product execution units is to be implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.
摘要翻译：通过构成与单指令多数据（SIMD）兼容的浮点内部产品执行单元，从而提高操作处理能力，可以提高其操作并行性水平的数据处理器。要实现一个可以显着提高每个指令的运行并行性水平，同时保持浮点长度为4的矢量内积执行单元的效率的操作系统。即使在广泛的操作系统可用的情况下，浮点长度-4向量内积执行单元也以最小宽度（单精度为32位）定义，并组成内部产品执行单元与SIMD兼容。内部产品执行单元和SIMD兼容组合的相互增强效应显着提高了操作并行性的水平。组合浮点长度-4向量内积执行单元，以计算长度为4的向量的内积和与SIMD并行的标量并行的标量之和，得到每周期32 FLOPS的处理能力。

10. 发明申请

US20060004985A1 Vector SIMD processor 有权
公开(公告)号：US20060004985A1
公开(公告)日：2006-01-05
申请号：US11212736
申请日：2005-08-29
申请人： Fumio Arakawa , Tetsuya Yamada
发明人： Fumio Arakawa , Tetsuya Yamada
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F7/483 , G06F7/5443 , G06F9/3877 , G06F9/3887 , G06F15/8023 , G06F15/8092
摘要： A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining the efficiency of the floating-point length-4 vector inner product execution units is to be implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.

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