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    • 5. 发明专利
    • Manufacturing method of transistor
    • 晶体管的制造方法
    • JP2004349583A
    • 2004-12-09
    • JP2003146907
    • 2003-05-23
    • Masashi KawasakiHideo OnoSharp Corpシャープ株式会社英男 大野雅司 川崎
    • HARA TAKESHIFUJITA TATSUYAOCHI HISAOYOSHIOKA HIROTOSUGIHARA TOSHINORIKAWASAKI MASASHIONO HIDEO
    • H01L29/786H01L21/336
    • PROBLEM TO BE SOLVED: To provide a method of manufacturing a bottom gate type transistor without damaging zinc oxide and without deteriorating indication quality using an ink jet method which is simple in operation and advantageous in cost when the zinc oxide is employed as a semiconductor element. SOLUTION: The manufacturing method of a bottom gate type transistor is adapted such that a gate electrode 11 is formed on a glass substrate 10 into a predetermined shape, and then a gate insulating film 12 is laminated, on which film 12 a source electrode 13 and a drain electrode 14 are in turn disposed. In the manufacturing method, the source electrode 13 and the drain electrode 14 are formed into predetermined shapes, and then a channel layer 15 containing the zinc oxide is formed into a predetermined shape with an ink jet method. COPYRIGHT: (C)2005,JPO&NCIPI
    • 解决的问题:提供一种制造底栅型晶体管的方法,而不损害氧化锌并且不会使用使用简单操作的喷墨方法而劣化指示质量,并且当将氧化锌用作 半导体元件。 解决方案:底栅型晶体管的制造方法适于使得栅极电极11形成在玻璃基板10上成为预定形状,然后层叠栅极绝缘膜12,其上膜12为源极 电极13和漏电极14依次设置。 在制造方法中,将源电极13和漏电极14形成为规定的形状,然后利用喷墨法将含有氧化锌的沟道层15形成为规定的形状。 版权所有(C)2005,JPO&NCIPI
    • 7. 发明专利
    • Oxide semiconductor light emitting element and its processing method
    • 氧化物半导体发光元件及其加工方法
    • JP2004335712A
    • 2004-11-25
    • JP2003129129
    • 2003-05-07
    • Masashi KawasakiSharp Corpシャープ株式会社雅司 川崎
    • SAITO HAJIMEKAWASAKI MASASHI
    • H01L21/3065H01L21/306H01L33/06H01L33/12H01L33/14H01L33/28H01L33/40H01L33/46H01S5/327H01L33/00
    • PROBLEM TO BE SOLVED: To provide an oxide semiconductor light emitting element which has excellent light emitting characteristics and in which a manufacturing yield is high and reliability is high, and to provide a method for processing the same. SOLUTION: An n-type ZnO buffer layer 102, an n-type Mg 0.1 Zn 0.9 O clad layer 103, an n-type ZnO light guide layer 104, a quantum well active layer 105, a p-type ZnO light guide layer 106, a p-type Mg 0.1 Zn 0.9 O first clad layer 107, an MG 0.15 Zn 0.85 O etching stop layer 108, a p-type Mg 0.1 Zn 0.9 O clad layer 109, and a p-type ZnO contact layer 110, are sequentially laminated in this order on an n-type ZnO single crystal substrate 101. The MG 0.15 Zn 0.85 O etching stop layer 108 is doped with N as an acceptor impurity in the concentration of 5×10 19 cm -3 , and is doped with Ga as a donor impurity in the concentration of 1×10 17 cm -3 . COPYRIGHT: (C)2005,JPO&NCIPI
    • 解决的问题:提供发光特性优异且制造成品率高,可靠性高的氧化物半导体发光元件,并提供其加工方法。 解决方案:n型ZnO缓冲层102,n型Mg 0.1 0.9 O覆层103,n型ZnO导光层104 ,量子阱有源层105,p型ZnO导光层106,p型Mg <0.1> Zn 0.9 O第一覆盖层107,MG 0.05 Sn蚀刻阻挡层108,p型Mg 0.1 0.9 O覆层109,以及 p型ZnO接触层110依次顺序层叠在n型ZnO单晶衬底101上.G0S0S0S0S0S0S0S0蚀刻停止层108为 掺杂有浓度为5×10 3 3的N作为受主杂质,并且以1×10 5的浓度掺杂有作为施主杂质的Ga, SP> 17 厘米 -3 。 版权所有(C)2005,JPO&NCIPI
    • 8. 发明专利
    • Semiconductor device and its manufacturing method
    • 半导体器件及其制造方法
    • JP2004319673A
    • 2004-11-11
    • JP2003110059
    • 2003-04-15
    • Masashi KawasakiHideo OnoSharp Corpシャープ株式会社英男 大野雅司 川崎
    • YOSHIOKA HIROTOSUGIHARA TOSHINORIFUJITA TATSUYAKAWASAKI MASASHIONO HIDEO
    • H01L21/28H01L21/336H01L29/417H01L29/423H01L29/49H01L29/786
    • PROBLEM TO BE SOLVED: To provide a semiconductor device of high reliability which is provided with a field effect type thin film transistor wherein the interface of a semiconductor layer and a gate insulating layer is suitably controlled.
      SOLUTION: The semiconductor device is provided with a substrate 1, a source electrode 2 and a drain electrode 3 which are formed on the substrate 1, a semiconductor layer 6 which is in contact with at least a part of an upper surface of the source electrode 2 and at least a part of an upper surface of the drain electrode 3, a gate electrode 9 which is formed on the semiconductor layer 6 and covers the semiconductor layer 6, and a gate insulating layer 11 formed between the semiconductor layer 6 and the gate electrode 9. The gate insulating layer 11 is provided with at least a first insulating layer 7 in contact with the upper surface of the semiconductor layer 6, and a second insulating layer 8 formed on the first insulating layer 7 which has an almost identical form to the semiconductor layer 6. The second insulating layer 8 has an almost identical form to the gate electrode 9.
      COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:提供一种高可靠性的半导体器件,其具有适当地控制半导体层和栅极绝缘层的界面的场效应型薄膜晶体管。 解决方案:半导体器件设置有形成在基板1上的基板1,源电极2和漏电极3,与基板1的上表面的至少一部分接触的半导体层6 源电极2和漏电极3的上表面的至少一部分,形成在半导体层6上并覆盖半导体层6的栅电极9以及形成在半导体层6之间的栅极绝缘层11 栅电极9.栅绝缘层11设置有至少与半导体层6的上表面接触的第一绝缘层7和形成在第一绝缘层7上的第二绝缘层8,第二绝缘层8具有几乎 第二绝缘层8具有与栅电极9几乎相同的形式。版权所有(C)2005,JPO&NCIPI
    • 10. 发明专利
    • Oxide semiconductor light emitting element
    • JP2004200389A
    • 2004-07-15
    • JP2002366841
    • 2002-12-18
    • Masashi KawasakiSharp Corpシャープ株式会社雅司 川崎
    • SAITO HAJIMEKAWASAKI MASASHI
    • H01S5/347
    • PROBLEM TO BE SOLVED: To obtain an oxide semiconductor light emitting element that can form a reflection end face by a simple method and has improved optical characteristics and reliability.
      SOLUTION: An n-type buffer layer 2, an n-type cladding layer 3, an n-type light guide layer 4, a non-doped quantum well active layer 5, a p-type light guide layer 6, a p-type cladding layer 7, and a p-type contact layer 8, are laminated on an n-type ZnO single-crystal substrate 1 with (1 -1 0 0) surface as a growth surface by a ZnO-based semiconductor. A ridge stripe in the direction of [1 1 -2 0] is formed on the contact layer 8 and the cladding layer 7. A (1 1 -2 0) surface vertical to the ridge stripe is subjected to cleavage to form a light reflection end face. As a result, by setting two mutually orthogonal easy cleavage surfaces that are easy cleavage surfaces to be the growth surface and the reflection end face, the reflection end face can be formed by simple cleavage. As a result, as compared with a comparison example where the reflection end face is formed by dry etching, an oscillation threshold current can be decreased by 30%, and element lifetime can be increased by five times.
      COPYRIGHT: (C)2004,JPO&NCIPI