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1. 发明授权

US07934198B2 Prefix matching structure and method for fast packet switching 失效
标题翻译：用于快速分组交换的前缀匹配结构和方法
公开(公告)号：US07934198B2
公开(公告)日：2011-04-26
申请号：US10968460
申请日：2004-10-18
申请人： Frederick R. Gruner , Gaurav Singh , Elango Ganesan , Samir C. Vora , Christopher M. Eccles , Brian Hang Wai Yang
发明人： Frederick R. Gruner , Gaurav Singh , Elango Ganesan , Samir C. Vora , Christopher M. Eccles , Brian Hang Wai Yang
IPC分类号： G06F9/44 , H04L12/28
CPC分类号： H04L29/12801 , H04L29/12009 , H04L45/00 , H04L45/7457 , H04L61/6004
摘要： A prefix matching apparatus for directing information to a destination port includes a memory configured to store a piece of data including an address and a plurality of levels each including a plurality of memory locations, the levels each representing a unique address space. A controller is coupled to the memory and to the plurality of levels, and is configured to read the data address and to direct the data to the next level associated with a unique address space associated with the data address. In one embodiment, the controller is configured to match the data address prefix to a plurality of addresses associated with the unique address spaces. Advantages of the invention include fast switch decisions and low switch latency.
摘要翻译：用于将信息引导到目的地端口的前缀匹配装置包括被配置为存储包括地址和多个级别的数据的存储器，每个级别包括多个存储器位置，每个级别表示唯一的地址空间。控制器耦合到存储器和多个电平，并且被配置为读取数据地址并将数据引导到与与数据地址相关联的唯一地址空间相关联的下一级。在一个实施例中，控制器被配置为将数据地址前缀匹配到与唯一地址空间相关联的多个地址。本发明的优点包括快速切换决定和低开关等待时间。

2. 发明授权

US06574758B1 Testing a bus coupled between two electronic devices 有权
标题翻译：测试一个耦合在两个电子设备之间的总线
公开(公告)号：US06574758B1
公开(公告)日：2003-06-03
申请号：US09522629
申请日：2000-03-10
申请人： Christopher M. Eccles
发明人： Christopher M. Eccles
IPC分类号： G06F1100
CPC分类号： G06F11/273 , G06F11/263
摘要： A bus coupled between two circuits (which may be, for example, each implemented as a single chip) is tested by transmitting from a first circuit a predetermined signal on the bus, and recognizing in the second circuit receipt of the predetermined signal. The predetermined signal indicates the beginning of a sequence of test signals that are transmitted therebetween. When any test signal in the sequence is not received correctly, an error signal is generated to specifically identify the test signal that failed, thereby to identify a faulty line in the bus. In one implementation, test signals in the sequence differ each from the other in just the location of a predetermined pattern of bits. For example, a bit pattern 1010 may be located in the beginning, middle or end of three signals of such a sequence. Therefore, in one embodiment, logic in each circuit simply shifts the bits of the predetermined pattern through different positions to obtain the first and second test signals, and such a sequence is called a “walking pattern.”
摘要翻译：耦合在两个电路之间的总线（其可以例如被实现为单个芯片）通过从第一电路在总线上发送预定信号并且在第二电路中识别预定信号来进行测试。预定信号表示在它们之间传输的测试信号序列的开始。当序列中的任何测试信号未正确接收时，产生错误信号以专门识别失败的测试信号，从而识别总线中的故障线路。在一个实现中，序列中的测试信号在预定的比特模式的位置中彼此不同。例如，位模式1010可以位于这种序列的三个信号的开始，中间或结束处。因此，在一个实施例中，每个电路中的逻辑简单地将预定模式的位移动到不同的位置以获得第一和第二测试信号，并且这样的序列被称为“行走模式”。

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