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1. 发明授权

US06519711B1 Method and apparatus for controlling a clocked circuit having a register for storing a bit received from an input terminal and an output terminal connected to clock terminal of the clocked circuit 有权
标题翻译：用于控制时钟电路的方法和装置具有用于存储从输入端接收的位的寄存器和连接到时钟电路的时钟端的输出端
公开(公告)号：US06519711B1
公开(公告)日：2003-02-11
申请号：US09409309
申请日：1999-09-29
申请人： Frederick H. Fischer , Srinivasa Gutta , Vladimir Sindalovsky
发明人： Frederick H. Fischer , Srinivasa Gutta , Vladimir Sindalovsky
IPC分类号： G06F104
CPC分类号： G06F1/08
摘要： A method and apparatus for controlling a clock of a component of an integrated circuit for testing purposes. The clock is controlled on a hardware level. Specifically, a stepped clocking technique is provided by which a processor can advance the clock signal of a component one bit at a time or in rapid bursts of successive bits. This provides for operation of the accelerator block in increments of half-clock cycles (bit by bit). The accelerator block can be stopped during processing of the dataset. Registers of the accelerator block can then be interrogated by the processor, which continues to operate at full clock speed, to determine how the accelerator block is processing the data.
摘要翻译：一种用于控制用于测试目的的集成电路的部件的时钟的方法和装置。时钟在硬件级别进行控制。具体地说，提供了一种阶梯式时钟技术，通过该阶梯式时钟技术，处理器可以一次一个位或者连续位的快速突发中提前一个分量的时钟信号。这提供了以半时钟周期（逐位）为增量的加速器块的操作。加速器块可以在处理数据集时停止。然后可以由继续以全时钟速度运行的处理器询问加速器块的寄存器，以确定加速器块如何处理数据。

2. 发明申请

US20130009679A1 BANG-BANG PHASE DETECTOR WITH HYSTERESIS 审中-公开
标题翻译： BANG-BANG相位检测器与HYSTERESIS
公开(公告)号：US20130009679A1
公开(公告)日：2013-01-10
申请号：US13178812
申请日：2011-07-08
申请人： Vladimir Sindalovsky , Lane A. Smith , Jung Cho
发明人： Vladimir Sindalovsky , Lane A. Smith , Jung Cho
IPC分类号： H03L7/06
CPC分类号： H03L7/00 , H03L7/06 , H03L7/08
摘要： In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state.
摘要翻译：在所描述的实施例中，具有数字爆炸相位检测器（BBPD）的时钟对准系统采用数字实现的滞后。第一个BBPD被用于相位控制环路，该相位控制环路比较来自两个不同时钟域源的相位，其中一个时钟源源作为相位控制环路的参考时钟。采用具有延迟参考时钟的第二个BBPD来解决第一个BBPD所看到的模糊相位关系。检查被定义为第一BBPD和第二BBPD的当前值的矢量的BBPD矢量的初始状态。基于BBPD矢量的初始状态和后续状态，允许非参考时钟通过相位控制回路的动作自然地移动到锁定状态，或者被迫使其相位顺时针或逆时针旋转以达到锁定状态。

3. 发明授权

US08067966B2 Voltage controlled delay loop and method with injection point control 有权
标题翻译：电压控制延时回路和注入点控制方法
公开(公告)号：US08067966B2
公开(公告)日：2011-11-29
申请号：US10999900
申请日：2004-11-30
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/087 , H04L7/0337
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟环包括多个延迟元件; 以及输入，其选择性地将参考时钟注入到所述多个延迟元件中的任一个中。多个延迟元件串联连接，例如循环。在一个示例性实现中，每个延迟元件具有相关联的多路复用器，其选择参考时钟之一和来自先前延迟元件的信号。

4. 发明申请

US20110274143A1 SPREAD SPECTRUM CLOCK SIGNAL GENERATOR METHOD AND SYSTEM 有权
标题翻译：传播频谱信号发生器方法和系统
公开(公告)号：US20110274143A1
公开(公告)日：2011-11-10
申请号：US12774175
申请日：2010-05-05
申请人： Joseph Anidjar , Parag Parikh , Vladimir Sindalovsky
发明人： Joseph Anidjar , Parag Parikh , Vladimir Sindalovsky
IPC分类号： H04B1/69 , H03D3/24
CPC分类号： H04B1/69 , H03B23/00
摘要： A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit clock generated by the PLL circuit. A repetition number divider computes the repetition number for each time slot in a piece-wise SSC modulation profile. A noise shaping modulator can be employed for modulating a fractional part associated with the repetition number. A repetition counter and a phase accumulator receives an integer part of the repetition number and counts unit interval clock periods equal to a sum of integer and the sigma-delta modulated fractional parts of the repetition number. The phase accumulator can be incremented and/or decremented based on the sign of the spread spectrum direction.
摘要翻译：一种用于产生具有作为重复数的函数的常数ppm偏移的扩频时钟信号的系统和方法。可以与锁相环电路相关联地配置相位插值器，以便提供由PLL电路产生的位时钟的相位移动。重复数字分频器计算分段SSC调制曲线中每个时隙的重复数。可以采用噪声整形调制器来调制与重复数相关联的分数部分。重复计数器和相位累加器接收重复数的整数部分，并且计数等于整数和重复数的Σ-Δ调制小数部分之和的单位间隔时钟周期。相位累加器可以根据扩频方向的符号递增和/或递减。

5. 发明授权

US07965133B2 Compensation techniques for reducing power consumption in digital circuitry 有权
标题翻译：用于降低数字电路功耗的补偿技术
公开(公告)号：US07965133B2
公开(公告)日：2011-06-21
申请号：US12160373
申请日：2007-10-31
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/00369
摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要翻译：用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作采样电路在指定的PVT条件范围内。数字电路从第二电源电压工作。

6. 发明申请

US20100290513A1 METHOD AND APPARATUS FOR INTEGRAL STATE INITIALIZATION AND QUALITY OF LOCK MONITORING IN A CLOCK AND DATA RECOVERY SYSTEM 有权
标题翻译：综合状态初始化和时钟和数据恢复系统中的监控质量的方法与装置
公开(公告)号：US20100290513A1
公开(公告)日：2010-11-18
申请号：US12846390
申请日：2010-07-29
申请人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
发明人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
IPC分类号： H04B17/00
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译：提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。

7. 发明授权

US07773667B2 Pseudo asynchronous serializer deserializer (SERDES) testing 有权
标题翻译：伪异步串行器解串器（SERDES）测试
公开(公告)号：US07773667B2
公开(公告)日：2010-08-10
申请号：US11181286
申请日：2005-07-14
申请人： Vladimir Sindalovsky , Lane A. Smith , Ronald Lamar Freyman , Max Jay Olsen
发明人： Vladimir Sindalovsky , Lane A. Smith , Ronald Lamar Freyman , Max Jay Olsen
IPC分类号： H04B3/46 , H04B17/00 , H04Q1/20
CPC分类号： G01R31/31715
摘要： The various embodiments of the invention provide an apparatus, system and method of asynchronous testing a serializer and deserializer data communication apparatus (SERDES) for determining frequency and phase locking to pseudo asynchronous input data having a continual phase offset. An exemplary apparatus includes a data sampler adapted to sample input serial data and to provide output data; a controlled tap delay with a selected tap having a phase offset from the input serial data, in which the selected tap is selectively coupleable to the data sampler to provide pseudo asynchronous input serial data; a first variable delay control adapted to delay a reference frequency provided to the controlled tap delay in response to the pseudo asynchronous input serial data; and a second delay control adapted to adjust the plurality of taps in response to the pseudo asynchronous input serial data. In additional embodiments, the pseudo asynchronous input serial data is provided from an interpolated phase from at least two selected taps.
摘要翻译：本发明的各种实施例提供了用于确定频率和相位锁定到具有连续相位偏移的伪异步输入数据的串行器和解串器数据通信装置（SERDES）的异步测试的装置，系统和方法。示例性装置包括适于对输入串行数据进行采样并提供输出数据的数据采样器; 具有与输入串行数据相位偏移的所选抽头的受控抽头延迟，其中所选择的抽头选择性地耦合到数据采样器以提供伪异步输入串行数据; 第一可变延迟控制器，其适于响应于所述伪异步输入串行数据延迟提供给受控抽头延迟的参考频率; 以及适于响应于所述伪异步输入串行数据来调整所述多个抽头的第二延迟控制。在另外的实施例中，伪异步输入串行数据从来自至少两个选择的抽头的内插相位提供。

8. 发明授权

US07711043B2 Method and apparatus for determining latch position for decision-feedback equalization using single-sided eye 失效
标题翻译：用于使用单面眼确定用于判决反馈均衡的闩锁位置的方法和装置
公开(公告)号：US07711043B2
公开(公告)日：2010-05-04
申请号：US11540946
申请日：2006-09-29
申请人： Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization. A threshold position of a latch employed by a decision-feedback equalizer is determined by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; and determining a threshold position of the latch based on the samples. The constrained input data can comprise (i) transitions from a binary value of 1 to a binary value of 0 or 1; or (ii) transitions from a binary value of 0 to a binary value of 0 or 1. The size of the single-sided data eye can be obtained by analyzing a histogram associated with the single-sided data eye to identify a region having a constant hit count.
摘要翻译：提供了用于确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。通过约束输入数据来确定由判决反馈均衡器采用的锁存器的阈值位置，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 以及基于所述样本确定所述锁存器的阈值位置。受约束的输入数据可以包括（i）从二进制值1到二进制值0或1的转换; 或（ii）从二进制值0到二进制值0或1的转换。单面数据眼的大小可以通过分析与单面数据眼相关联的直方图来识别具有不断的命中数。

9. 发明申请

US20090175395A1 DATA ALIGNMENT METHOD FOR ARBITRARY INPUT WITH PROGRAMMABLE CONTENT DESKEWING INFO 有权
标题翻译：具有可编程内容描述信息的仲裁输入的数据对齐方法
公开(公告)号：US20090175395A1
公开(公告)日：2009-07-09
申请号：US11969440
申请日：2008-01-04
申请人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
发明人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H04L7/005 , H04L7/04
摘要： In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.
摘要翻译：在示例性实施例中，数据对准系统包括先进先出寄存器（FIFO），连接到FIFO的可编程模式发生器和连接到可编程模式发生器和FIFO的控制器。 FIFO被配置为向具有一个或多个通道的串行数据链路的第一数据通道提供数据或从其接收数据。串行数据链路的每个数据通道被配置为发送相应的串行数据流。可编程模式发生器被配置为生成多个对准符号。控制器被配置为管理串行数据链路的一个或多个数据通道的对准以及将多个对准符号中选择的一个对准符号插入到每个串行数据流中。

10. 发明授权

US07425856B2 Phase interpolator with output amplitude correction 有权
标题翻译：具有输出幅度校正的相位内插器
公开(公告)号：US07425856B2
公开(公告)日：2008-09-16
申请号：US11479749
申请日：2006-06-30
申请人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
发明人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
IPC分类号： H03H11/16
CPC分类号： H03K5/13 , H03K2005/00052 , H03K2005/00156 , H03K2005/00195
摘要： A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.
摘要翻译：相位插值器从两个相位偏移输入时钟信号A和B产生相位插值输出时钟信号Z，其中输出时钟的插值角基于权重值W.相位内插器具有A侧和B- 每个电路具有（1）并联电流镜阵列，（2）一组并联开关，其中每个开关与相应的电流镜串联连接，以及（3）编码器，其基于重量值W.通过相位内插器的总电流随内插角度变化，使得例如，具有内插角度的输出幅度的变化减小。通常，重量值W中的各个位值不用于控制各个开关的所有插补角度。

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