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1. 发明授权

US07425856B2 Phase interpolator with output amplitude correction 有权
标题翻译：具有输出幅度校正的相位内插器
公开(公告)号：US07425856B2
公开(公告)日：2008-09-16
申请号：US11479749
申请日：2006-06-30
申请人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
发明人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
IPC分类号： H03H11/16
CPC分类号： H03K5/13 , H03K2005/00052 , H03K2005/00156 , H03K2005/00195
摘要： A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.
摘要翻译：相位插值器从两个相位偏移输入时钟信号A和B产生相位插值输出时钟信号Z，其中输出时钟的插值角基于权重值W.相位内插器具有A侧和B- 每个电路具有（1）并联电流镜阵列，（2）一组并联开关，其中每个开关与相应的电流镜串联连接，以及（3）编码器，其基于重量值W.通过相位内插器的总电流随内插角度变化，使得例如，具有内插角度的输出幅度的变化减小。通常，重量值W中的各个位值不用于控制各个开关的所有插补角度。

2. 发明申请

US20080001644A1 Phase interpolator with output amplitude correction 有权
公开(公告)号：US20080001644A1
公开(公告)日：2008-01-03
申请号：US11479749
申请日：2006-06-30
申请人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
发明人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , H03K2005/00052 , H03K2005/00156 , H03K2005/00195
摘要： A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

3. 发明授权

US07236037B2 Alternating clock signal generation for delay loops 失效
标题翻译：用于延迟环的交替时钟信号生成
公开(公告)号：US07236037B2
公开(公告)日：2007-06-26
申请号：US11138777
申请日：2005-05-26
申请人： Christopher J. Abel , Vladimir Sindalovsky , Craig B. Ziemer
发明人： Christopher J. Abel , Vladimir Sindalovsky , Craig B. Ziemer
IPC分类号： H03K3/00
CPC分类号： H04L7/0025 , H03L7/07 , H03L7/0814 , H04L7/0337
摘要： A delay loop (e.g., a voltage-controlled delay loop) has (at least) two devices (e.g., interpolators) for generating clock signals for injection into the delay elements of the delay loop in a leap-frog manner, in which, while one interpolator is generating the clock signal currently selected for injection, the other interpolator can be controlled to generate the next clock signal to be selected for injection. This leap-frog technique can provide more settling time for generating injected clock signals than implementations that rely on a single interpolator.
摘要翻译：延迟环路（例如，电压控制延迟环路）具有（至少）两个用于产生用于以跳跃方式注入到延迟环路的延迟元件中的时钟信号的器件（例如，内插器），其中，一个内插器正在产生当前被选择用于注入的时钟信号，另一个内插器可被控制以产生要被选择用于注入的下一个时钟信号。这种跳跃式技术可以提供更多的建立时间来产生注入的时钟信号，而不是依赖于单个内插器的实现。

4. 发明授权

US07778377B2 Methods and apparatus for spread spectrum generation using a voltage controlled delay loop 有权
标题翻译：使用电压控制延迟环路进行扩频生成的方法和装置
公开(公告)号：US07778377B2
公开(公告)日：2010-08-17
申请号：US11141695
申请日：2005-05-31
申请人： Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03D3/24
CPC分类号： H04B15/02 , H04B2215/067
摘要： Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.
摘要翻译：提供了用于产生具有与参考频率的预定义偏移的频率的方法和装置。公开了一种扩频发生器电路，其包括用于产生具有不同相位的多个信号的电压控制延迟环路; 以及至少一个内插器，用于处理至少两个所述信号以产生具有所述至少两个所述信号的相位之间的相位的输出信号，其中所述输出在所述至少两个信号的相位之间变化生成扩频。使用连续的相位延迟增加来产生频率低于所施加的时钟信号的扩展频谱，并且使用连续的相位延迟减小产生具有高于时钟信号的频率的扩频。

5. 发明授权

US07190198B2 Voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟回路
公开(公告)号：US07190198B2
公开(公告)日：2007-03-13
申请号：US10999889
申请日：2004-11-30
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03L7/06
CPC分类号： G06F1/04
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟回路包括至少一个延迟元件以产生参考时钟的至少两个相位; 中央内插器，用于内插参考时钟的至少两个相位以产生内插信号; 以及将内插信号注入延迟级的输入。中央插值器提供精细的相位控制。此外，可以通过选择性地将内插信号注入到给定的延迟级中来可选地实现粗略的相位控制。公开了使用多个内插器的粗略和精细相位控制的另一个电压控制延迟回路。

6. 发明授权

US07787515B2 Method and apparatus for generation of asynchronous clock for spread spectrum transmission 有权
标题翻译：用于产生扩频传输的异步时钟的方法和装置
公开(公告)号：US07787515B2
公开(公告)日：2010-08-31
申请号：US11353431
申请日：2006-02-14
申请人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , William B. Wilson , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , William B. Wilson , Craig B. Ziemer
IPC分类号： H04B1/00
CPC分类号： H04L27/0014 , H04B1/7075 , H04L2027/0036
摘要： A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.
摘要翻译：用于扩频率控制的电路使用第一内插器在第一信号和第二信号之间进行相位插值，并且基于第一控制信号产生第一输出信号。第二内插器用于在第三信号和第四信号之间进行相位插值，并且基于第二控制信号产生第二输出信号。多路复用器用于基于选择信号选择第一输出信号或第二输出信号作为扩频时钟（SSCLK）。跳跃内插器控制用于与SSCLK同步地产生基于第一类型的相位调整请求的第一控制信号，基于第二类型的相位调整请求的第二控制信号，以及选择信号在改变第一控制信号或第二控制信号之后允许内插器稳定时间之后，在第一输出信号和第二输出信号之间切换多路复用器。

7. 发明授权

US07312667B2 Statically controlled clock source generator for VCDL clock phase trimming 失效
标题翻译：用于VCDL时钟相位修整的静态时钟源发生器
公开(公告)号：US07312667B2
公开(公告)日：2007-12-25
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03B27/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.
摘要翻译：本发明解决了用于微调VCDL延迟线输出时钟的受控时钟源的产生。在这个修整过程中，对这些输出时钟的静态变化进行调整。本发明使用受控的时钟源消除了对该修整过程的实时性的需要，并且降低了所需电路的费用。

8. 发明授权

US08422536B2 Spread spectrum clock signal generator method and system 有权
标题翻译：扩频时钟信号发生器的方法和系统
公开(公告)号：US08422536B2
公开(公告)日：2013-04-16
申请号：US12774175
申请日：2010-05-05
申请人： Joseph Anidjar , Parag Parikh , Vladimir Sindalovsky
发明人： Joseph Anidjar , Parag Parikh , Vladimir Sindalovsky
IPC分类号： H04B1/69
CPC分类号： H04B1/69 , H03B23/00
摘要： A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit clock generated by the PLL circuit. A repetition number divider computes the repetition number for each time slot in a piece-wise SSC modulation profile. A noise shaping modulator can be employed for modulating a fractional part associated with the repetition number. A repetition counter and a phase accumulator receives an integer part of the repetition number and counts unit interval clock periods equal to a sum of integer and the sigma-delta modulated fractional parts of the repetition number. The phase accumulator can be incremented and/or decremented based on the sign of the spread spectrum direction.
摘要翻译：一种用于产生具有作为重复数的函数的常数ppm偏移的扩频时钟信号的系统和方法。可以与锁相环电路相关联地配置相位插值器，以便提供由PLL电路产生的位时钟的相位移动。重复数字分频器计算分段SSC调制曲线中每个时隙的重复数。可以采用噪声整形调制器来调制与重复数相关联的分数部分。重复计数器和相位累加器接收重复数的整数部分，并且计数等于整数和重复数的Σ-Δ调制小数部分之和的单位间隔时钟周期。相位累加器可以根据扩频方向的符号递增和/或递减。

9. 发明申请

US20100244937A1 Compensation Techniques for Reducing Power Consumption in Digital Circuitry 有权
标题翻译：降低数字电路功耗的补偿技术
公开(公告)号：US20100244937A1
公开(公告)日：2010-09-30
申请号：US12160373
申请日：2007-10-31
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/00369
摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要翻译：用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作采样电路在指定的PVT条件范围内。数字电路从第二电源电压工作。

10. 发明授权

US07330060B2 Method and apparatus for sigma-delta delay control in a delay-locked-loop 失效
标题翻译：延迟锁定环路中Σ-Δ延迟控制的方法和装置
公开(公告)号：US07330060B2
公开(公告)日：2008-02-12
申请号：US11221387
申请日：2005-09-07
申请人： Christopher J. Abel , Abhishek Duggal , Peter C. Metz , Vladimir Sindalovsky
发明人： Christopher J. Abel , Abhishek Duggal , Peter C. Metz , Vladimir Sindalovsky
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/089 , H03L7/093
摘要： Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.
摘要翻译：提供了延迟锁定环中的Σ-Δ延迟控制的方法和装置，其采用延迟线来基于参考信号产生时钟信号。如果时钟信号相对于参考信号具有时间导通，则产生第一值; 并且如果时钟信号相对于参考信号具有时滞，则产生第二值。累积第一和第二值以产生N位数字字; 并将N位数字字减少为M位数字字，其中M小于N.此后，M位数字字可以转换为模拟偏置信号。还原步骤可以由例如Σ-Δ调制器进行。可以使用低通滤波器对由Σ-Δ调制器产生的高频量化噪声进行滤波。转换步骤可以由诸如主/从数字模拟转换器之类的数 - 模转换器执行。

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