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1. 发明授权

US5066998A Severable conductive path in an integrated-circuit device 失效
标题翻译：集成电路器件中的可切断导电路径
公开(公告)号：US5066998A
公开(公告)日：1991-11-19
申请号：US569755
申请日：1990-08-20
申请人： Frederick H. Fischer , Kuo-hua Lee , William J. Nagy , Nur Selamoglu
发明人： Frederick H. Fischer , Kuo-hua Lee , William J. Nagy , Nur Selamoglu
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L23/5256 , H01L21/76888 , H01L2924/0002
摘要： Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.
摘要翻译：集成电路器件设置有导电路径或链路，通过激光照射或电流脉冲可以切断或融合。为了便于定影，优选的连接部分的厚度局部减小，例如，通过采用两层层压和蚀刻步骤如下：首先，将一层导体材料沉积在电介质表面上，并局部减小厚度通过在被选择进行熔化的一个或几个点处进行蚀刻，以及其次沉积另外的导体材料层，然后蚀刻以产生通过这些点的期望的导电路径。

2. 发明授权

US5185291A Method of making severable conductive path in an integrated-circuit device 失效
标题翻译：在集成电路器件中制造可分离的导电路径的方法
公开(公告)号：US5185291A
公开(公告)日：1993-02-09
申请号：US755702
申请日：1991-09-06
申请人： Frederick H. Fischer , Kuo-hua Lee , William J. Nagy , Nur Selamoglu
发明人： Frederick H. Fischer , Kuo-hua Lee , William J. Nagy , Nur Selamoglu
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L21/76888 , H01L23/5256 , H01L2924/0002 , Y10S148/055
摘要： Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.
摘要翻译：集成电路器件设置有导电路径或链路，通过激光照射或电流脉冲可以切断或融合。为了便于定影，优选的连接部分的厚度局部减小，例如，通过采用两层层压和蚀刻步骤如下：首先，将一层导体材料沉积在电介质表面上，并局部减小厚度通过在被选择进行熔化的一个或几个点处进行蚀刻，以及其次沉积另外的导体材料层，然后蚀刻以产生通过这些点的期望的导电路径。

3. 发明授权

US4810049A Reducing bend and coupling losses in integrated optical waveguides 失效
标题翻译：降低集成光波导中的弯曲和耦合损耗
公开(公告)号：US4810049A
公开(公告)日：1989-03-07
申请号：US34128
申请日：1987-04-02
申请人： Frederick H. Fischer , Edmond J. Murphy , Trudie C. Rice
发明人： Frederick H. Fischer , Edmond J. Murphy , Trudie C. Rice
IPC分类号： G02B6/125 , G02B6/12
CPC分类号： G02B6/125
摘要： A groove is disposed in a substrate longitudinally along the outside radius of a bent integrated optical waveguide to constrain the mode of optical energy propagating therein such that the optical energy that would normally be radiated is confined to the waveguide, thereby reducing transmission loss through the bend. Further, to reduce coupling loss between an integrated optical waveguide and an optical fiber, two grooves are disposed longitudinally along either side of the integrated optical waveguide to constrain the mode of optical energy propagating in the waveguide to approximate the mode of the optical energy propagating in the optical fiber. To further reduce both bend and coupling losses, the ends of the grooves bend away from the waveguide.

4. 发明授权

US5623449A Flag detection for first-in-first-out memories 失效
标题翻译：针对先进先出存储器的标志检测
公开(公告)号：US5623449A
公开(公告)日：1997-04-22
申请号：US514199
申请日：1995-08-11
申请人： Frederick H. Fischer , Kenneth D. Fitch
发明人： Frederick H. Fischer , Kenneth D. Fitch
IPC分类号： G06F12/16 , G06F5/12 , G06F11/10 , G06F11/30 , G06F12/00 , G11C7/00 , G11C29/00
CPC分类号： G06F11/1008
摘要： A technique is provided for setting an error status bit in a first-in, first-out memory having data words with associated error bits. When a word having an associated error bit that is set to indicate an error is written into the FIFO, the write pointer is captured, and a flag is set, indicating that the FIFO has a word with an error. If a second word is written which has an error, that pointer value is captured, overwriting the current value. As the FIFO is read, the read pointers are compared with the captured write pointer. When the values are equal, and the FIFO is read, the flag is cleared, indicating that there are no more errors in the FIFO. In an exemplary case, each word in the FIFO has 8 data bits and 3 error bits. A FIFO used in implementing a UART in a modem typically includes 16 or 32 words.
摘要翻译：提供了一种用于在具有相关联的错误位的数据字的先进先出存储器中设置错误状态位的技术。当将具有指示错误的关联错误位的字写入FIFO时，捕获写指针，并且设置标志，指示FIFO具有错误的字。如果写入了具有错误的第二个字，则捕获该指针值，从而覆盖当前值。读取FIFO时，读取指针与捕获的写入指针进行比较。当值相等并且FIFO被读取时，该标志被清除，表示FIFO中没有更多的错误。在一个示例性情况下，FIFO中的每个字都有8个数据位和3个错误位。用于在调制解调器中实现UART的FIFO通常包括16或32个字。

5. 发明授权

US4598039A Formation of features in optical material 失效
标题翻译：形成光学材料的特征
公开(公告)号：US4598039A
公开(公告)日：1986-07-01
申请号：US627025
申请日：1984-07-02
申请人： Frederick H. Fischer , Edmond J. Murphy , Trudie C. Rice
发明人： Frederick H. Fischer , Edmond J. Murphy , Trudie C. Rice
IPC分类号： B23K26/00 , B23K26/18 , B23K26/40 , B44B7/00 , G02B6/122 , G02B6/36 , G02B6/42 , G03C5/00
CPC分类号： G02B6/1221 , B23K26/362 , B23K26/40 , B23K26/402 , B44B7/00 , G02B6/3636 , G02B6/3688 , B23K2201/35 , B23K2203/16 , B23K2203/30 , B23K2203/36 , B23K2203/50 , B23K2203/52 , G02B6/3652 , G02B6/4224 , Y10S430/146
摘要： A laser or other source of radiant electromagnetic energy removes optically transparent material (e.g., LiNbO.sub.3) to form various structures. To enhance coupling the radiant energy to the optical material, a layer of an ablative absorber (e.g., a metal or organic material) can be used. Alternately, the radiant source can be initially operated above a threshold that causes removal of a surface layer of the optical material. After selectively thus removing a surface layer of the optical material, subsequent sub-threshold applications of radiant energy remove additional optical material due to a change in the underlying material, rendering it more absorptive at the wavelength of the electromagnetic energy. Optical devices, including waveguides, can be formed, as well as isolation grooves, alignment structures, etc.
摘要翻译：激光或其他辐射电磁能源消除光学透明材料（例如LiNbO 3）以形成各种结构。为了将辐射能耦合到光学材料，可以使用消融吸收体（例如，金属或有机材料）的层。或者，辐射源可以首先在导致去除光学材料的表面层的阈值以上操作。在选择性地因此去除光学材料的表面层之后，辐射能量的后续次级阈值应用由于下层材料的变化而移除附加的光学材料，使得其在电磁能的波长处更吸收。可以形成包括波导在内的光学器件，以及隔离槽，对准结构等。

6. 发明授权

US06255869B1 Method and apparatus for system resource negotiation 有权
标题翻译：系统资源协商的方法和装置
公开(公告)号：US06255869B1
公开(公告)日：2001-07-03
申请号：US09407413
申请日：1999-09-29
申请人： Frederick H. Fischer
发明人： Frederick H. Fischer
IPC分类号： G06F1300
CPC分类号： G11C8/16
摘要： A method and apparatus for negotiating access to a shared resource by two independent domains. A request register is provided to each domain for receiving an ownership request signal. Request signals received from both domains are clock-synchronized and fed to a cross-coupled circuit. The cross-coupled circuit includes two blocks, each having a switch and a register for receiving a request signal. The registers are responsive to different portions of a clock cycle, e.g., rising and falling edges. The switch in each block receives a signal from one domain on one input and a signal from the output of the register in the same block on the other input. The switch of one block is controlled by the output signal of the register of the other block. The output of one of the blocks is used to control a domain switch to permit data streams from the independent domains to reach the shared resource. Each domain requests use of the shared resource by sending a request signal to its respective request register. The cross-coupled circuit negotiates ownership and controls the domain switch. Simultaneous requests are time-separated due to the clock-phase based nature of the cross-coupled circuit.
摘要翻译：一种用于通过两个独立域协商对共享资源的访问的方法和装置。向每个域提供请求寄存器以接收所有权请求信号。从两个域接收的请求信号是时钟同步的，并被馈送到交叉耦合电路。交叉耦合电路包括两个块，每个块具有开关和用于接收请求信号的寄存器。寄存器响应于时钟周期的不同部分，例如上升沿和下降沿。每个块中的开关从一个输入上的一个域接收信号，并在另一个输入上从同一块中的寄存器的输出接收信号。一个块的开关由另一个块的寄存器的输出信号控制。其中一个块的输出用于控制域交换机以允许来自独立域的数据流到达共享资源。每个域通过向其相应的请求寄存器发送请求信号来请求共享资源的使用。交叉耦合电路协商所有权并控制域交换机。由于交叉耦合电路的基于时钟相位的特性，同时请求是时间分隔的。

7. 发明授权

US4853758A Laser-blown links 失效
标题翻译：激光连接
公开(公告)号：US4853758A
公开(公告)日：1989-08-01
申请号：US84531
申请日：1987-08-12
申请人： Frederick H. Fischer
发明人： Frederick H. Fischer
IPC分类号： H01L21/82 , H01L23/525 , H01L27/10
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： An improved technique for blowing conductive links with a laser provides for a wider range of acceptable laser energies. The link in an upper interconnect level is placed on a pedestal, typically formed by etching away a thin layer of the underlying dielectric on which the conductive link is formed. A link in a lower interconnect level thereby has the thickness of the dielectric overlying it reduced. This has been found to reduce the minimum laser energy required to cleanly blow the links in both levels and to reduce the effect of link orientation on the required laser energy.

8. 发明授权

US06833286B2 Semiconductor device with variable pin locations 有权
标题翻译：具有可变引脚位置的半导体器件
公开(公告)号：US06833286B2
公开(公告)日：2004-12-21
申请号：US10218783
申请日：2002-08-14
申请人： Frederick H. Fischer , Kenneth D. Fitch , Ho T. Nguyen , Scott A. Segan
发明人： Frederick H. Fischer , Kenneth D. Fitch , Ho T. Nguyen , Scott A. Segan
IPC分类号： H01L2144
CPC分类号： G11C5/066 , G11C29/1201
摘要： An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.
摘要翻译：一种包括逻辑电路，多个引脚和将逻辑电路耦合到多个引脚的接口单元的半导体器件，其中接口单元允许任何引脚耦合到逻辑电路的任何部分。半导体器件提供了一种模板，通过该模板可以制造具有不同引脚分配的许多不同类型的半导体器件，而不需要改变生产掩模。

9. 发明授权

US06347387B1 Test circuits for testing inter-device FPGA links including a shift register configured from FPGA elements to form a shift block through said inter-device FPGA links 失效
标题翻译：用于测试设备间FPGA链路的测试电路，包括由FPGA元件配置的移位寄存器，以通过所述设备间FPGA链路形成移位块
公开(公告)号：US06347387B1
公开(公告)日：2002-02-12
申请号：US09169848
申请日：1998-10-09
申请人： Frederick H. Fischer
发明人： Frederick H. Fischer
IPC分类号： G01R3128
CPC分类号： G06F11/263 , G06F11/277
摘要： A test device for testing inter-device connections of field programmable gate arrays (FPGAS) by using the FPGAs themselves during testing to form a shift register. Particularly, the shift register comprises flip-flops and buffers interconnected by the actual FPGA inter-device or inter-device connections under test. A control circuit generates an input test pattern which is serially input into one end of the shift register and read out of the other end. The input pattern and the output pattern are compared to determine if they match. If they match, there are no faults through the interconnections used in the shift register. The shift register also may be bidirectional such that the input and output patterns are read in and out at the same terminal.
摘要翻译：一种用于在测试期间通过使用FPGA本身来形成移位寄存器来测试现场可编程门阵列（FPGAS）的器件间连接的测试装置。特别地，移位寄存器包括通过实际的FPGA器件间或被测器件间连接互连的触发器和缓冲器。控制电路产生输入测试图案，其输入到移位寄存器的一端并从另一端读出。比较输入模式和输出模式，以确定它们是否匹配。如果它们匹配，则通过移位寄存器中使用的互连没有故障。移位寄存器也可以是双向的，使得输入和输出模式在同一个终端读出。

10. 发明授权

US06519711B1 Method and apparatus for controlling a clocked circuit having a register for storing a bit received from an input terminal and an output terminal connected to clock terminal of the clocked circuit 有权
标题翻译：用于控制时钟电路的方法和装置具有用于存储从输入端接收的位的寄存器和连接到时钟电路的时钟端的输出端
公开(公告)号：US06519711B1
公开(公告)日：2003-02-11
申请号：US09409309
申请日：1999-09-29
申请人： Frederick H. Fischer , Srinivasa Gutta , Vladimir Sindalovsky
发明人： Frederick H. Fischer , Srinivasa Gutta , Vladimir Sindalovsky
IPC分类号： G06F104
CPC分类号： G06F1/08
摘要： A method and apparatus for controlling a clock of a component of an integrated circuit for testing purposes. The clock is controlled on a hardware level. Specifically, a stepped clocking technique is provided by which a processor can advance the clock signal of a component one bit at a time or in rapid bursts of successive bits. This provides for operation of the accelerator block in increments of half-clock cycles (bit by bit). The accelerator block can be stopped during processing of the dataset. Registers of the accelerator block can then be interrogated by the processor, which continues to operate at full clock speed, to determine how the accelerator block is processing the data.
摘要翻译：一种用于控制用于测试目的的集成电路的部件的时钟的方法和装置。时钟在硬件级别进行控制。具体地说，提供了一种阶梯式时钟技术，通过该阶梯式时钟技术，处理器可以一次一个位或者连续位的快速突发中提前一个分量的时钟信号。这提供了以半时钟周期（逐位）为增量的加速器块的操作。加速器块可以在处理数据集时停止。然后可以由继续以全时钟速度运行的处理器询问加速器块的寄存器，以确定加速器块如何处理数据。

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