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1. 发明申请

US20050009280A1 Methods of fabricating multiple sets of field effect transistors 失效
公开(公告)号：US20050009280A1
公开(公告)日：2005-01-13
申请号：US10914825
申请日：2004-08-09
申请人： Fred Fishburn , Martin Roberts
发明人： Fred Fishburn , Martin Roberts
IPC分类号： H01L21/8234 , H01L21/8238 , H01L39/22
CPC分类号： H01L21/31053 , H01L21/32139 , H01L21/82345 , H01L21/823828 , H01L21/823842 , Y10S438/941
摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

2. 发明申请

US20050009278A1 Methods of fabricating multiple sets of field effect transistors 有权
公开(公告)号：US20050009278A1
公开(公告)日：2005-01-13
申请号：US10914821
申请日：2004-08-09
申请人： Fred Fishburn , Martin Roberts
发明人： Fred Fishburn , Martin Roberts
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/32139 , H01L21/82345 , H01L21/823828 , H01L21/823842 , Y10S438/941
摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

3. 发明申请

US20060166445A1 Methods of fabricating multiple sets of field effect transistors 有权
公开(公告)号：US20060166445A1
公开(公告)日：2006-07-27
申请号：US11386167
申请日：2006-03-21
申请人： Fred Fishburn , Martin Roberts
发明人： Fred Fishburn , Martin Roberts
IPC分类号： H01L21/8234
CPC分类号： H01L21/31053 , H01L21/32139 , H01L21/82345 , H01L21/823828 , H01L21/823842 , Y10S438/941
摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

4. 发明申请

US20050009279A1 Methods of fabricating multiple sets of field effect transistors 失效
标题翻译：制造多组场效应晶体管的方法
公开(公告)号：US20050009279A1
公开(公告)日：2005-01-13
申请号：US10914822
申请日：2004-08-09
申请人： Fred Fishburn , Martin Roberts
发明人： Fred Fishburn , Martin Roberts
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L21/31053 , H01L21/32139 , H01L21/82345 , H01L21/823828 , H01L21/823842 , Y10S438/941
摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.
摘要翻译：本发明包括制造多组场效应晶体管的方法。在一个实施方案中，在绝缘覆盖层上形成蚀刻停止层，所述绝缘覆盖层形成在形成在衬底上的导电栅极层上。蚀刻停止层，绝缘覆盖层和导电栅极层被图案化和蚀刻以在衬底上形成第一组导电栅极结构。在第一组栅极结构上形成并平坦化介电材料。此后，对绝缘覆盖层和导电栅极层进行构图和蚀刻，以在衬底上形成第二组导电栅极结构。考虑了其他方面和实现。

5. 发明授权

US07473644B2 Method for forming controlled geometry hardmasks including subresolution elements 有权
标题翻译：用于形成受控几何硬掩模的方法，包括分解元件
公开(公告)号：US07473644B2
公开(公告)日：2009-01-06
申请号：US10883215
申请日：2004-07-01
申请人： Richard H. Lane , Fred Fishburn
发明人： Richard H. Lane , Fred Fishburn
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high aspect ratio features in the underlying substrate. Some disclosed methods also enable simultaneous formation of hardmask structures of various dimensions, of both conventional and subresolution size, to enable etching structural features of different sizes in the underlying substrate.
摘要翻译：在诸如硅晶片或石英衬底之类的衬底上形成硬掩模材料的准确的对称横截面间隔物的方法，用于形成用于形成集成电路的精确的子分辨特征。所得到的对称硬掩模间隔物与其对称的上部可用于精确地蚀刻底层基底中的良好限定的高纵横比特征。一些公开的方法还能够同时形成具有常规和亚分辨率尺寸的各种尺寸的硬掩模结构，以使得能够蚀刻下面的衬底中的不同尺寸的结构特征。

6. 发明授权

US07268039B2 Method of forming a contact using a sacrificial structure 有权
标题翻译：使用牺牲结构形成接触的方法
公开(公告)号：US07268039B2
公开(公告)日：2007-09-11
申请号：US11706690
申请日：2007-02-15
申请人： Fred Fishburn , Forest Chen , John M. Drynan
发明人： Fred Fishburn , Forest Chen , John M. Drynan
IPC分类号： H01L21/8242
CPC分类号： H01L21/7687 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L28/84 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.
摘要翻译：使用至少一种牺牲结构形成双面电容器的方法，例如牺牲衬垫或牺牲插塞。在半导体晶片上的绝缘层中的至少一个开口的侧壁上形成牺牲衬垫。然后在牺牲衬垫上形成第一导电层。然后选择性地去除牺牲衬垫以暴露第一导电层的第一表面，而不损坏半导体晶片上的暴露部件。去除牺牲衬垫形成与第一导电层的第一表面相邻的开放空间。在开放空间中形成介电层和第二导电层，产生双面电容器。还公开了形成具有增加的电容和接触的双面电容器的方法。此外，还公开了包括至少一个牺牲结构的中间半导体器件结构。

7. 发明授权

US07157324B2 Transistor structure having reduced transistor leakage attributes 有权
标题翻译：晶体管结构具有减小的晶体管泄漏属性
公开(公告)号：US07157324B2
公开(公告)日：2007-01-02
申请号：US10931513
申请日：2004-09-01
申请人： Vishnu K. Agarwal , Fred Fishburn , Rongsheng Yang , Howard E. Rhodes , Jeffrey A. McKee
发明人： Vishnu K. Agarwal , Fred Fishburn , Rongsheng Yang , Howard E. Rhodes , Jeffrey A. McKee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823481 , H01L21/76232
摘要： Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposited thereon, defines the process stack. The dopant is selected having the same n- or p-typing as the substrate. Through etching, the first and second layers of the process stack become pulled back from a trench wall of the substrate to form the implant region. Occupation of the implant region by the dopant prevents undesirable transistor leakage because the electrical characteristics of the implant region are so significantly changed, in comparison to central areas of the substrate underneath the first layer, that the threshold voltage of the implant region is raised to be about equivalent to or greater than the substantially uniform threshold voltage in the central area.
摘要翻译：在具有通过拉回工艺叠层的第一层和第二层而形成的掺杂注入区的衬底中，晶体管结构中不期望的晶体管泄漏变得大大降低。衬底的一部分也具有沉积在其上的第一和第二层，限定了工艺叠层。掺杂剂选择具有与底物相同的n-或p-型。通过蚀刻，工艺堆叠的第一和第二层从衬底的沟槽壁拉回以形成植入区域。由掺杂剂对植入区域的占用防止了不期望的晶体管泄漏，因为与第一层下方的衬底的中心区域相比，注入区域的电特性如此显着地改变，使植入区域的阈值电压升高到约等于或大于中心区域中的基本均匀的阈值电压。

8. 发明申请

US20060220087A1 METHOD OF FORMING A CONTACT STRUCTURE INCLUDING A VERTICAL BARRIER STRUCTURE AND TWO BARRIER LAYERS 审中-公开
标题翻译：形成接触结构的方法，包括垂直障碍物结构和两个障碍层
公开(公告)号：US20060220087A1
公开(公告)日：2006-10-05
申请号：US11421406
申请日：2006-05-31
申请人： Fred Fishburn
发明人： Fred Fishburn
IPC分类号： H01L29/94
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/7687 , H01L21/76877 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. In an alternate embodiment, a contact structure is fabricated by forming a polysilicon layer on a substrate, forming a tungsten nitride layer above the polysilicon layer, and etching the polysilicon layer and the tungsten nitride layer to a level below the surface of a substrate structure. A silicon nitride layer is formed above the tungsten nitride layer, and a ruthenium silicide layer is formed above the silicon nitride layer. The ruthenium silicide layer is then polished.
摘要翻译：本发明涉及用于集成电路的接触结构和制造接触结构的方法。在一个实施例中，接触结构包括导电层，形成在导电层之上的一个或多个阻挡层，以及环绕多晶硅层和一个或多个阻挡层的阻挡结构。在替代实施例中，通过在衬底上形成多晶硅层，在多晶硅层上形成氮化钨层，并将多晶硅层和氮化钨层蚀刻到衬底结构表面以下的水平来制造接触结构。在氮化硅层之上形成氮化硅层，在氮化硅层的上方形成硅化钌层。然后抛光钌化硅层。

9. 发明申请

US20060160296A1 Methods of forming CMOS constructions 有权
标题翻译：形成CMOS结构的方法
公开(公告)号：US20060160296A1
公开(公告)日：2006-07-20
申请号：US11353592
申请日：2006-02-14
申请人： Luan Tran , Fred Fishburn
发明人： Luan Tran , Fred Fishburn
IPC分类号： H01L21/8238
CPC分类号： H01L21/7681 , H01L21/76895 , H01L21/823475
摘要： The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.
摘要翻译：本发明包括用于形成与半导体结构相关联的电连接的方法。提供一种半导体衬底，其具有其上的导电线，并且具有与导电线相邻的至少两个扩散区域。在扩散区域上形成图案化的蚀刻停止层。图案化蚀刻停止件具有延伸穿过其的一对开口，其中开口沿着大致平行于该线的轴线。在蚀刻停止点上形成绝缘材料。绝缘材料暴露于蚀刻以在绝缘材料内形成沟槽，并且将开口从蚀刻停止件延伸到扩散区域。沟槽的至少一部分直接在开口上方并且沿着线的轴线延伸。在开口内和沟槽内形成导电材料。

10. 发明申请

US20060110920A1 Low temperature nitride used as cu barrier layer 有权
公开(公告)号：US20060110920A1
公开(公告)日：2006-05-25
申请号：US11328865
申请日：2006-01-09
申请人： Zhiping Yin , Eden Zielinski , Fred Fishburn
发明人： Zhiping Yin , Eden Zielinski , Fred Fishburn
IPC分类号： H01L21/44 , H01L21/471
CPC分类号： H01L23/53238 , C23C16/345 , H01L21/3185 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.

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