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1. 发明申请

US20060110920A1 Low temperature nitride used as cu barrier layer 有权
公开(公告)号：US20060110920A1
公开(公告)日：2006-05-25
申请号：US11328865
申请日：2006-01-09
申请人： Zhiping Yin , Eden Zielinski , Fred Fishburn
发明人： Zhiping Yin , Eden Zielinski , Fred Fishburn
IPC分类号： H01L21/44 , H01L21/471
CPC分类号： H01L23/53238 , C23C16/345 , H01L21/3185 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.

2. 发明授权

US07186642B2 Low temperature nitride used as Cu barrier layer 有权
标题翻译：低温氮化物用作Cu阻挡层
公开(公告)号：US07186642B2
公开(公告)日：2007-03-06
申请号：US11328865
申请日：2006-01-09
申请人： Zhiping Yin , Eden Zielinski , Fred Fishburn
发明人： Zhiping Yin , Eden Zielinski , Fred Fishburn
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , C23C16/345 , H01L21/3185 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.
摘要翻译：在金属表面上沉积非导电阻挡层的方法，其中金属的电阻在非导电阻挡层沉积之前和之后基本保持不变。沉积工艺提供了低温处理环境，以便抑制在金属中形成诸如硅化物的杂质，其中硅化物可以不利地增加下面的金属的电阻。

3. 发明授权

US06984893B2 Low temperature nitride used as Cu barrier layer 有权
公开(公告)号：US06984893B2
公开(公告)日：2006-01-10
申请号：US10303585
申请日：2002-11-22
申请人： Zhiping Yin , Eden Zielinski , Fred Fishburn
发明人： Zhiping Yin , Eden Zielinski , Fred Fishburn
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , C23C16/345 , H01L21/3185 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.

4. 发明授权

US06492267B1 Low temperature nitride used as Cu barrier layer 有权
标题翻译：低温氮化物用作Cu阻挡层
公开(公告)号：US06492267B1
公开(公告)日：2002-12-10
申请号：US09503105
申请日：2000-02-11
申请人： Zhiping Yin , Eden Zielinski , Fred Fishburn
发明人： Zhiping Yin , Eden Zielinski , Fred Fishburn
IPC分类号： H01L2144
CPC分类号： H01L23/53238 , C23C16/345 , H01L21/3185 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.
摘要翻译：在金属表面上沉积非导电阻挡层的方法，其中金属的电阻在非导电阻挡层沉积之前和之后基本保持不变。沉积工艺提供了低温处理环境，以便抑制在金属中形成诸如硅化物的杂质，其中硅化物可以不利地增加下面的金属的电阻。

5. 发明申请

US20120256309A1 Integrated Circuit Having Pitch Reduced Patterns Relative To Photolithography Features 失效
标题翻译：具有相对于光刻特征的节距减小的集成电路
公开(公告)号：US20120256309A1
公开(公告)日：2012-10-11
申请号：US13530679
申请日：2012-06-22
申请人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L23/48
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.
摘要翻译：具有不同尺寸特征的集成电路，其中较小特征与具有通过常规光刻形成的尺寸的较大特征具有间距倍增关系。

6. 发明授权

US08129093B2 Prevention of photoresist scumming 有权
标题翻译：防止光刻胶浮渣
公开(公告)号：US08129093B2
公开(公告)日：2012-03-06
申请号：US12761151
申请日：2010-04-15
申请人： Zhiping Yin , Jingyi Bai
发明人： Zhiping Yin , Jingyi Bai
IPC分类号： G03F7/26
CPC分类号： G03F7/11 , G03F7/0045 , G03F7/091
摘要： A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid level, and thus causes resist scumming. An increased acid layer beneath the resist prevents acid diffusion. In one embodiment, the increased acid layer is a layer of spun-on acid or PAG dissolved in aqueous solution. In another embodiment, the increased acid layer is a hard mask material with a PAG or an acid mixed into the material. The high acid content inhibits the diffusion of acid from the photoresist into neighboring layers, and thus substantially reduces photoresist scumming and footing.
摘要翻译：使用光酸产生剂（PAG）或酸来降低抗污垢和基底。酸从光致抗蚀剂扩散到邻居会导致酸水平降低，从而导致抗污垢浮渣。抗蚀剂下面的增加的酸层防止酸扩散。在一个实施方案中，增加的酸层是溶解在水溶液中的纺丝酸或PAG层。在另一个实施方案中，增加的酸层是具有混合到该材料中的PAG或酸的硬掩模材料。高酸含量抑制酸从光致抗蚀剂扩散到相邻层中，从而基本上减少光致抗蚀剂的浮渣和基底。

7. 发明申请

US20110019051A1 IMAGE SENSORS WITH PIXEL CHARGE SUMMING 有权
标题翻译：图像传感器与像素充电夏季
公开(公告)号：US20110019051A1
公开(公告)日：2011-01-27
申请号：US12509398
申请日：2009-07-24
申请人： Zhiping Yin , John W. Ladd
发明人： Zhiping Yin , John W. Ladd
IPC分类号： H04N5/335
CPC分类号： H04N5/378 , H04N5/347 , H04N9/07
摘要： An image sensor has an array of pixels of different colors. The pixels may be arranged in a repeating pattern of eight pixels having four rows and two columns. During charge summing operations, the first and third rows may share a floating diffusion and the second and fourth rows may share a floating diffusion. When charge summing is inactive, transfer gates in the first and second columns may be controlled independently, while transfer gates in pairs of rows may be controlled simultaneously. When charge summing is active, summed charges from pixels of the same color in the first and third rows may be placed on the floating diffusion shared by the first and third rows and summed charges from pixels of the same color in the second and fourth rows may be placed on the floating diffusion shared by the second and fourth rows.
摘要翻译：图像传感器具有不同颜色的像素阵列。像素可以以具有四行和两列的八个像素的重复图案布置。在电荷求和操作期间，第一和第三行可以共享浮动扩散，并且第二和第四行可以共享浮动扩散。当电荷求和不活动时，可以独立地控制第一和第二列中的传输门，同时可以同时控制成对行的传输门。当充电求和有效时，第一和第三行中相同颜色的像素的相加电荷可以被放置在由第一和第三行共享的浮动扩散上，并且第二行和第四行中相同颜色的像素的相加电荷可以放置在由第二和第四行共享的浮动扩散上。

8. 发明授权

US07804115B2 Semiconductor constructions having antireflective portions 有权
标题翻译：具有抗反射部分的半导体结构
公开(公告)号：US07804115B2
公开(公告)日：2010-09-28
申请号：US11482244
申请日：2006-07-07
申请人： Richard Holscher , Zhiping Yin , Tom Glass
发明人： Richard Holscher , Zhiping Yin , Tom Glass
IPC分类号： H01L31/062 , C09K19/00
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/3086 , Y10T428/1086
摘要： In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. The layer of photoresist is patterned. A portion of the antireflective material layer unmasked by the patterned layer of photoresist is removed. In another aspect, the invention includes the following semiconductor processing. An antireflective material layer is formed over a substrate. The antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. Portions of the layer of photoresist are exposed to radiation waves. Some of the radiation waves are absorbed by the antireflective material during the exposing.
摘要翻译：一方面，本发明包括半导体处理方法。在基板上形成防反射材料层。抗反射材料层的至少一部分在大于约400℃的温度下退火。在退火的抗反射材料层上形成一层光致抗蚀剂。图案化光刻胶层。除去由图案化的光致抗蚀剂层掩蔽的抗反射材料层的一部分。另一方面，本发明包括以下半导体处理。在基板上形成防反射材料层。抗反射材料层在大于约400℃的温度下退火。在退火的抗反射材料层上形成一层光致抗蚀剂。光致抗蚀剂层的一部分暴露于辐射波。一些辐射波在曝光期间被抗反射材料吸收。

9. 发明授权

US07659630B2 Interconnect structures with interlayer dielectric 失效
标题翻译：互连结构与层间电介质
公开(公告)号：US07659630B2
公开(公告)日：2010-02-09
申请号：US11841180
申请日：2007-08-20
申请人： Zhiping Yin , Mark E. Jost
发明人： Zhiping Yin , Mark E. Jost
IPC分类号： H01L21/31
CPC分类号： H01L21/76849 , H01L21/76801 , H01L21/76867
摘要： The present invention relates to metallic interconnect having an interlayer dielectric thereover, the metallic interconnect having an upper surface substantially free from oxidation. The metallic interconnect may have an exposed upper surface thereon that is passivated by a nitrogen containing compound.
摘要翻译：本发明涉及在其上具有层间电介质的金属互连，金属互连具有基本上没有氧化的上表面。金属互连可以在其上具有被含氮化合物钝化的暴露的上表面。

10. 发明授权

US07651951B2 Pitch reduced patterns relative to photolithography features 失效
公开(公告)号：US07651951B2
公开(公告)日：2010-01-26
申请号：US11681027
申请日：2007-03-01
申请人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

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