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    • 7. 发明申请
    • REFERENCE CLOCK RE-TIMING SCHEME IN ELECTRONIC CIRCUITS
    • 电子电路中的参考时钟重新排列方案
    • US20130211758A1
    • 2013-08-15
    • US13397551
    • 2012-02-15
    • Indu PrathapanKrishnasawamy NagarajFrank Zhang
    • Indu PrathapanKrishnasawamy NagarajFrank Zhang
    • G06F19/00
    • H03L7/091H03L2207/50
    • A phase detector includes a counter to generate the integer portion of a number of complete cycles of an output clock at each active edge of a reference clock. A time to digital converter in the phase detector generates the fractional portion of the number of complete cycles of the output clock at each active edge of the reference clock. The sum of the fractional portion and the integer portion is subtracted from an accumulated value obtained by accumulating a pre-determined number to generate an error signal as the output of the phase detector. The counter is read at an active edge of one of two re-timed clocks derived from the reference clock. Each of the two re-timed clocks is generated based on a comparison of the fractional portion with a pair of thresholds. Errors due to metastability in reading the counter are thereby avoided.
    • 相位检测器包括计数器,用于在参考时钟的每个有效边沿处产生输出时钟的多个完整周期的整数部分。 相位检测器中的数字时钟转换器在参考时钟的每个有效边沿产生输出时钟的完整周期数的小数部分。 从通过累加预定数量获得的累积值中减去分数部分和整数部分的和,以产生作为相位检测器的输出的误差信号。 在从参考时钟导出的两个定时时钟之一的有效边沿读取计数器。 基于小数部分与一对阈值的比较来生成两个重新定时时钟中的每一个。 从而避免了由于读取计数器而产生亚稳定的错误。
    • 9. 发明授权
    • Systems and methods for reducing circuit area
    • 降低电路面积的系统和方法
    • US07847667B2
    • 2010-12-07
    • US11943287
    • 2007-11-20
    • Peter R. KingetFrank Zhang
    • Peter R. KingetFrank Zhang
    • H01F5/00
    • H01L23/5227H01F2017/0046H01F2017/008H01F2021/125H01L27/0207H01L27/0727H01L28/10H01L2924/0002H01L2924/00
    • Methods and systems are provided for reducing circuit area. Some embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path crosses itself at least two points and wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane. Other embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane, and wherein the circuit comprises a signal path that is rake-shaped and crosses the path of the inductor at substantially perpendicular angles.
    • 提供了减少电路面积的方法和系统。 一些实施例提供了电子设备,其包括由具有两个端部的路径形成的电感器,所述两个端部基本围绕围绕中心区域的平面环绕,其中所述路径在至少两个点处与其自身交叉,并且其中所述路径限定所述电感器的外边界; 以及位于电感器的外边界内并且基本上在平面内或与平面相邻的电路。 其他实施例提供了电子设备,其包括由具有两个端部的路径形成的电感器,所述两个端部基本围绕围绕中心区域的平面环绕,其中所述路径限定所述电感器的外边界; 以及位于电感器的外边界内并且基本上在该平面内或与该平面相邻的电路,并且其中该电路包括一个信号路径,该信号路径是耙状的并以大致垂直的角度穿过该电感器的路径。