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1. 发明申请

US20100032727A1 BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HOT) DIRECT SILICON BONDED (DSB) SUBSTRATES 有权
标题翻译：混合定向技术（热）直接硅粘结（DSB）基板的边界区域缺陷减少
公开(公告)号：US20100032727A1
公开(公告)日：2010-02-11
申请号：US12538048
申请日：2009-08-07
申请人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
发明人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
IPC分类号： H01L27/092 , H01L21/20 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/187 , H01L21/324 , H01L21/76264 , H01L21/823807 , H01L21/823892 , H01L29/045 , H01L29/665
摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.
摘要翻译：用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。（100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。还公开了用本发明方法形成的集成电路。

2. 发明授权

US07855111B2 Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates 有权
标题翻译：混合取向技术（HOT）直接硅键合（DSB）衬底的边界区域缺陷减少
公开(公告)号：US07855111B2
公开(公告)日：2010-12-21
申请号：US12538048
申请日：2009-08-07
申请人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
发明人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
IPC分类号： H01L21/8238 , H01L27/118
CPC分类号： H01L21/26506 , H01L21/187 , H01L21/324 , H01L21/76264 , H01L21/823807 , H01L21/823892 , H01L29/045 , H01L29/665
摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.
摘要翻译：用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。（100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。还公开了用本发明方法形成的集成电路。

3. 发明授权

US08119470B2 Mitigation of gate to contact capacitance in CMOS flow 有权
标题翻译：栅极接触电容在CMOS流中的缓解
公开(公告)号：US08119470B2
公开(公告)日：2012-02-21
申请号：US11726253
申请日：2007-03-21
申请人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
发明人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
IPC分类号： H01L21/338 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/7833 , H01L21/76804 , H01L21/76897 , H01L29/6656 , H01L29/6659 , Y02P80/30
摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.
摘要翻译：主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。这种电容至少是不利的，因为它可以抑制晶体管的切换速度。因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。

4. 发明授权

US07396728B2 Methods of improving drive currents by employing strain inducing STI liners 有权
标题翻译：应用感应STI衬垫改善驱动电流的方法
公开(公告)号：US07396728B2
公开(公告)日：2008-07-08
申请号：US11170501
申请日：2005-06-29
申请人： Ajith Varghese , Narendra Singh Mehta , Jonathan McAulay Holt
发明人： Ajith Varghese , Narendra Singh Mehta , Jonathan McAulay Holt
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L21/823807 , H01L21/76224 , H01L21/823878
摘要： A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.
摘要翻译：一种方法形成包括选择性地将应变引入到NMOS和PMOS器件的有源区的隔离结构的半导体器件。在半导体体上形成硬掩模层。在暴露并限定隔离区域的硬掩模层上形成抗蚀剂层。图案化硬掩模层，并使用硬掩模层作为掩模形成沟槽区域。在PMOS区域的沟槽区域内形成有对PMOS区域的有源区域产生压缩应变的氧化物沟槽衬垫。在NMOS沟槽区域内形成氮化物沟槽衬垫，其将拉伸应变引入NMOS区域的有源区。

5. 发明申请

US20080006886A1 Semiconductor Device Manufactured Using a Non-Contact Implant Metrology 有权
标题翻译：使用非接触式种植体计量制造的半导体器件
公开(公告)号：US20080006886A1
公开(公告)日：2008-01-10
申请号：US11559271
申请日：2006-11-13
申请人： Narendra Mehta , Ajith Varghese , Benjamin Moser
发明人： Narendra Mehta , Ajith Varghese , Benjamin Moser
IPC分类号： H01L21/425 , H01L29/78
CPC分类号： H01L21/26513 , H01L21/31155 , H01L22/14
摘要： A method of manufacturing a semiconductor device including calibrating an ion implant process. The calibration includes forming a dielectric layer over a calibration substrate. A dopant is implanted into the dielectric layer. Charge is deposited on a surface of the dielectric layer, and voltage on the surface is measured. An electrical characteristic of the dielectric layer is determined, and a doping level of the dielectric layer is determined from the electrical characteristic. The electrical characteristic is associated with an operating set-point of the ion implant process. The calibrated ion implant process is used to implant the dopant into a semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，包括校准离子注入工艺。校准包括在校准基板上形成电介质层。将掺杂剂注入电介质层。电荷沉积在电介质层的表面上，并且测量表面上的电压。确定电介质层的电特性，根据电气特性确定电介质层的掺杂程度。电特性与离子注入工艺的操作设定点相关联。校准离子注入工艺用于将掺杂剂注入到半导体衬底中。

6. 发明申请

US20070004118A1 Methods of improving drive currents by employing strain inducing STI liners 有权
标题翻译：应用感应STI衬垫改善驱动电流的方法
公开(公告)号：US20070004118A1
公开(公告)日：2007-01-04
申请号：US11170501
申请日：2005-06-29
申请人： Ajith Varghese , Narendra Mehta , Jonathan Holt
发明人： Ajith Varghese , Narendra Mehta , Jonathan Holt
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76224 , H01L21/823878
摘要： A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.
摘要翻译：一种方法形成包括选择性地将应变引入到NMOS和PMOS器件的有源区的隔离结构的半导体器件。在半导体体上形成硬掩模层。在暴露并限定隔离区域的硬掩模层上形成抗蚀剂层。图案化硬掩模层，并使用硬掩模层作为掩模形成沟槽区域。在PMOS区域的沟槽区域内形成有对PMOS区域的有源区域产生压缩应变的氧化物沟槽衬垫。在NMOS沟槽区域内形成氮化物沟槽衬垫，其将拉伸应变引入NMOS区域的有源区。

7. 发明申请

US20080268627A1 TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL 有权
公开(公告)号：US20080268627A1
公开(公告)日：2008-10-30
申请号：US11742229
申请日：2007-04-30
申请人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
发明人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
IPC分类号： H01L21/425
CPC分类号： H01L21/324 , H01L21/265 , H01L21/26513 , H01L21/823412 , H01L21/823462 , H01L29/105 , H01L29/66477
摘要： A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

8. 发明申请

US20080268603A1 TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL 审中-公开
标题翻译：使用两步损伤天线的晶体管性能
公开(公告)号：US20080268603A1
公开(公告)日：2008-10-30
申请号：US11742186
申请日：2007-04-30
申请人： Hiroaki NIIMI , Jarvis Benjamin Jacobs , Ajith Varghese
发明人： Hiroaki NIIMI , Jarvis Benjamin Jacobs , Ajith Varghese
IPC分类号： H01L21/324 , H01L21/265
CPC分类号： H01L21/26513 , H01L21/324 , H01L27/1052
摘要： A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
摘要翻译：两步热处理方法包括在半导体器件的硅衬底中进行离子注入。在半导体器件上执行第一热处理程序。在半导体器件上连续执行第二热处理程序以减少由离子注入产生的损伤。

9. 发明申请

US20070054455A1 Method to obtain uniform nitrogen profile in gate dielectrics 有权
标题翻译：在栅极电介质中获得均匀氮分布的方法
公开(公告)号：US20070054455A1
公开(公告)日：2007-03-08
申请号：US11224219
申请日：2005-09-12
申请人： Ajith Varghese , Reima Laaksonen , Terrence Riley
发明人： Ajith Varghese , Reima Laaksonen , Terrence Riley
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/28194 , H01L21/823462 , H01L29/513 , H01L29/518 , Y10S438/981
摘要： The present invention provides, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160, 165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.
摘要翻译：本发明在一个方面提供一种制造微电子器件100的方法，该方法包括在衬底115上沉积第一栅极电介质层160，使第一栅极电介质层160经受第一氮化处理，形成第二栅极电介质层165，并且具有小于第一栅极电介质层160的厚度的厚度，以及使第一和第二栅极电介质层160,165进行第二次氮化处理，其中第一和第二次氮化处理是不同的。本发明还提供了一种根据该方法制造的微电子器件100。

10. 发明申请

US20070015347A1 Strain modulation employing process techniques for CMOS technologies 有权
标题翻译：采用CMOS技术的工艺技术进行应变调制
公开(公告)号：US20070015347A1
公开(公告)日：2007-01-18
申请号：US11183348
申请日：2005-07-18
申请人： Narendra Mehta , Wayne Bather , Ajith Varghese
发明人： Narendra Mehta , Wayne Bather , Ajith Varghese
IPC分类号： C12P21/06
CPC分类号： H01L21/823807 , H01L21/265 , H01L21/823878 , H01L29/7843 , H01L29/7846
摘要： A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the first and second regions. A mask is then formed that exposes the second region and covers the first region. A material is selected for a modification implant and the selected material is implanted into the second region thereby converting a portion of the modifiable tensile strain inducing layer into a compressive strain inducing layer within the PMOS region.
摘要翻译：一种方法形成包括可修改的应变诱导层的半导体器件。提供半导体本体。识别半导体主体的第一和第二区域。在第一和第二区域内的器件上形成可修改的拉伸应变诱导层。然后形成露出第二区域并覆盖第一区域的掩模。选择材料用于修改植入物，并且将所选择的材料注入第二区域，从而将可修改的拉伸应变诱导层的一部分转化为PMOS区域内的压缩应变诱导层。

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