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1. 发明授权

US07103816B2 Method and system for reducing test data volume in the testing of logic products 有权
公开(公告)号：US07103816B2
公开(公告)日：2006-09-05
申请号：US09768121
申请日：2001-01-23
申请人： Frank O. Distler , Leonard O. Farnsworth, III , Andrew Ferko , Brion L. Keller , Bernd K. Koenemann , Donald L. Wheater
发明人： Frank O. Distler , Leonard O. Farnsworth, III , Andrew Ferko , Brion L. Keller , Bernd K. Koenemann , Donald L. Wheater
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31921
摘要： A method and system for reducing test data volume in the testing of logic products such as integrated circuit chips. Test data loaded by a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. According to the invention, non-care bits in the test vector data are filled with repetitive background data to provide for a high degree of compressibility of the test vector data. A substantial portion of the care bits may also be set to a repetitive value and the original values later recovered.

2. 发明授权

US06782501B2 System for reducing test data volume in the testing of logic products 有权
标题翻译：用于在逻辑产品测试中减少测试数据量的系统
公开(公告)号：US06782501B2
公开(公告)日：2004-08-24
申请号：US09972000
申请日：2001-10-05
申请人： Frank O. Distler , L. Owen Farnsworth , Andrew Ferko , Brion L. Keller , Bernd K. Koenemann
发明人： Frank O. Distler , L. Owen Farnsworth , Andrew Ferko , Brion L. Keller , Bernd K. Koenemann
IPC分类号： G06F1100
CPC分类号： G01R31/31921
摘要： A system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips, and systems comprised of multiple integrated circuit chips. Test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. Non-care bits in the test vector data are filled with repetitive, repeating, or other background data sequences. The background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data. The recovery can use hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or software residing in the tester and operating while the test is performed. The software and/or hardware recover the full test input stimulus data including the fill data from the much more compact source data. The use of a compacted data format for the fill data provides for a high degree of compressibility of the total test input stimulus vector data set. The method for test data reduction combines the compact data representation for the input stimulus data with on-product or off-product compression of the test response data. The response data compression can be accomplished by the use of error-detecting codes, by comparing the responses from several identical products under test. The combination of data compression techniques for both, test input stimulus data and test output response data, results in significantly better overall data reduction.
摘要翻译：用于减少诸如集成电路芯片上的模块的逻辑产品测试以及由多个集成电路芯片组成的系统的测试数据量的系统。测试刺激数据从测试器加载到逻辑产品中以应用于其中的组合逻辑电路的部分，以便检测包括“关心”位和“非关心”位的故障。护理位目标是正在测试的逻辑电路中的感兴趣的焦点故障，而无关位不存在。测试向量数据中的非关心位填充有重复的，重复的或其他背景数据序列。构建背景数据序列使得它们可以从少量的初始化数据被算术地恢复。恢复可以使用位于被测产品，测试仪内部，被测产品和测试仪之间的硬件，或者测试仪中存在的软件，并在测试时进行操作。软件和/或硬件从更紧凑的源数据中恢复包括填充数据的完整测试输入激励数据。对于填充数据使用压缩数据格式提供了总测试输入刺激矢量数据集的高度可压缩性。测试数据简化的方法将输入激励数据的紧凑数据表示与测试响应数据的产品或产品外压缩相结合。响应数据压缩可以通过使用错误检测代码，通过比较来自几个相同的被测产品的响应来实现。用于测试输入刺激数据和测试输出响应数据的数据压缩技术的组合导致显着更好的整体数据减少。

3. 发明授权

US06708305B1 Deterministic random LBIST 失效
标题翻译：确定性随机LBIST
公开(公告)号：US06708305B1
公开(公告)日：2004-03-16
申请号：US09691370
申请日：2000-10-18
申请人： L. Owen Farnsworth , Brion L. Keller , Bernd K. Koenemann , Timothy J. Koprowski , Thomas J. Snethen , Donald L. Wheater
发明人： L. Owen Farnsworth , Brion L. Keller , Bernd K. Koenemann , Timothy J. Koprowski , Thomas J. Snethen , Donald L. Wheater
IPC分类号： G01R3128
CPC分类号： G01R31/318594 , G01R31/318552
摘要： Deterministic random Logic Built In Self Test (LBIST) is disclosed that applies Deterministic Stored Pattern Tests (DSPTs) by using random LBIST. Basically, the present invention selects the appropriate pseudorandom pattern for use with a scan cycle that needs care bits. The scan cycle may be a current or future scan cycle. In particular, the present invention determines care bits for a particular scan cycle. A pseudorandom pattern is generated that is then aligned with the particular scan cycle. If the pseudorandom pattern contains the care bits, with the correct values and in the proper positions within the pattern, this alignment tests one or more logic devices.
摘要翻译：公开了通过使用随机LBIST应用确定性存储模式测试（DSPT）的确定性随机逻辑内置自检（LBIST）。基本上，本发明选择适用于需要关心位的扫描周期使用的伪随机模式。扫描周期可能是当前或将来的扫描周期。特别地，本发明确定特定扫描周期的护理位。生成伪随机模式，然后将其与特定的扫描周期对准。如果伪随机模式包含护理位，具有正确的值并且在模式内的适当位置，则该对准测试一个或多个逻辑器件。

4. 发明授权

US07381986B2 Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer 有权
公开(公告)号：US07381986B2
公开(公告)日：2008-06-03
申请号：US11477963
申请日：2006-06-28
申请人： Brion L. Keller , Bernd K. F. Koenermann , David E. Lackey , Donald L. Wheater
发明人： Brion L. Keller , Bernd K. F. Koenermann , David E. Lackey , Donald L. Wheater
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/2889 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits. The stimulus busses can also be used to provide each chip with parallel serial scan data as well as power and other signals such as clock and enable and disable signals. Each chip control circuit provides the chip with power, bus clock, control, enable and response lines, can also connected to each chip via suitable lines in the kerfs.

5. 发明授权

US07435990B2 Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer 有权
标题翻译：用于在半导体晶片上并入的半导体芯片的测试装置
公开(公告)号：US07435990B2
公开(公告)日：2008-10-14
申请号：US10248380
申请日：2003-01-15
申请人： Brion L. Keller , Bernd K. F. Koenemann , David E. Lackey , Donald L. Wheater
发明人： Brion L. Keller , Bernd K. F. Koenemann , David E. Lackey , Donald L. Wheater
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/2889 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits. The stimulus busses can also be used to provide each chip with parallel serial scan data as well as power and other signals such as clock and enable and disable signals. Each chip control circuit provides the chip with power, bus clock, control, enable and response lines, can also connected to each chip via suitable lines in the kerfs.
摘要翻译：将提供用于同时测试半导体晶片上的多个未切割芯片的多个通信路径的装置，其将同时允许每个这样的通信路径在使用最少数量的测试器接触的同时服务多于一个芯片。本发明的这些和其它目的，特征和优点在其上具有多个切口隔离的集成芯片的半导体晶片中实现，每个所述芯片通过两个不同的刺激总线耦合到策略放置的管理电路中的至少两个不同的管理电路 ; 每个芯片通过布置在芯片之间的切口区域中的选择控制电路耦合到每个管理电路。正是这种冗余可以显着降低相关管理或选择控制电路故障的可能性。刺激总线还可以用于为每个芯片提供并行串行扫描数据以及功率和其他信号，如时钟和使能和禁止信号。每个芯片控制电路为芯片提供电源，总线时钟，控制，使能和响应线路，还可以通过切口中的适当线路连接到每个芯片。

6. 发明授权

US06804803B2 Method for testing integrated logic circuits 有权
标题翻译：集成逻辑电路测试方法
公开(公告)号：US06804803B2
公开(公告)日：2004-10-12
申请号：US09681438
申请日：2001-04-05
申请人： Carl F. Barnhart , Robert W. Bassett , Brion L. Keller , David E. Lackey , Mark R. Taylor , Donald L. Wheater
发明人： Carl F. Barnhart , Robert W. Bassett , Brion L. Keller , David E. Lackey , Mark R. Taylor , Donald L. Wheater
IPC分类号： G06F1100
CPC分类号： G06F11/263
摘要： A method of testing a circuit having multiple elements is disclosed. A plurality of faults representing the elements of the circuit for testing said circuit is created. The faults are grouped based on common attributes of the faults. A test pattern for each group of faults is created. Finally, the circuit is tested using test patterns for each group of faults.
摘要翻译：公开了一种测试具有多个元件的电路的方法。创建表示用于测试所述电路的电路元件的多个故障。故障根据故障的常见属性进行分组。创建每组故障的测试模式。最后，使用每组故障的测试模式对电路进行测试。

7. 发明授权

US5546408A Hierarchical pattern faults for describing logic circuit failure mechanisms 失效
标题翻译：用于描述逻辑电路故障机制的分层模式故障
公开(公告)号：US5546408A
公开(公告)日：1996-08-13
申请号：US257594
申请日：1994-06-09
申请人： Brion L. Keller
发明人： Brion L. Keller
IPC分类号： G01R31/3183 , G06F11/25 , G06F11/263
CPC分类号： G06F11/2257 , G01R31/318342
摘要： A method and system (12) for defining and using a pattern fault file (15) having a static pattern fault and/or a dynamic pattern fault. A static pattern fault is represented as a list of required excitation nodes and their values, as well as a fault propagation point. The fault propagation point is defined to be a net or node in a circuit to be tested where the defect's effect first appears once it has been excited. A dynamic pattern fault adds to this structure an initial value list of nodes and their required initial values. The dynamic-pattern fault is employed to advantage when a two pattern sequence is required to excite a specific defect. Logical combinations (AND/OR) of specified pin excitations and fault propagation points may be employed. The excitation value list, the initial value list and the propagation point can include any of the following: input pins of an entity; output pins of the entity; nets inside of the entity; pins on usage blocks inside the entity; nets inside a usage of a lower entity; and pins inside a usage of a lower level entity. The method and system also provide a capability to define pattern faults for each entity in a hierarchial circuit definition, and thus provides a mechanism to define pattern faults for specific cells in a cell technical library (13).
摘要翻译：一种用于定义和使用具有静态图案故障和/或动态图案故障的图案故障文件（15）的方法和系统（12）。静态图案故障表示为所需激励节点及其值的列表，以及故障传播点。故障传播点被定义为要被测试的电路中的网络或节点，其中缺陷的影响在激发之后首先出现。动态模式故障将此结构添加到节点的初始值列表及其所需的初始值。当需要两个图案序列来激发特定缺陷时，动态图案故障将被使用。可以使用指定的引脚激励和故障传播点的逻辑组合（AND / OR）。激励值列表，初始值列表和传播点可以包括以下任一项：实体的输入引脚; 实体的输出引脚; 实体内网; 实体内使用块的引脚; 网内使用较低的实体; 并在低级实体的使用中引脚。该方法和系统还提供了在分层电路定义中为每个实体定义模式故障的能力，并且因此提供了定义单元技术库（13）中特定小区的模式故障的机制。

8. 发明授权

US08296703B1 Fault modeling for state retention logic 有权
标题翻译：状态保留逻辑的故障建模
公开(公告)号：US08296703B1
公开(公告)日：2012-10-23
申请号：US12339958
申请日：2008-12-19
申请人： Krishna Chakravadhanula , Steven L. Gregor , Brion L. Keller , Vivek Chickermane
发明人： Krishna Chakravadhanula , Steven L. Gregor , Brion L. Keller , Vivek Chickermane
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G11C29/56008 , G06F2217/78
摘要： A method for modeling state-retention logic includes: specifying a circuit that includes an arrangement of circuit elements, wherein a portion of the circuit is organized into a power domain with a power-domain control for effecting power variations within the power domain, and the power domain includes a state-retention cell that includes a retention element with a retention-element control for saving state-retention-cell values in the retention element during power variations in the power domain; determining one or more pattern faults for detecting defects in state-retention operation of the circuit by associating circuit element values with values for the power-domain control or the retention-element control; and saving one or more values for the one or more pattern faults.
摘要翻译：一种用于建模状态保持逻辑的方法包括：指定包括电路元件布置的电路，其中电路的一部分被组织成具有功率域控制的功率域，以实现功率域内的功率变化，并且功率域包括状态保持单元，其包括具有保持元件控制的保持元件，用于在功率域的功率变化期间在保持元件中保持状态保持单元值; 通过将电路元件值与功率域控制或保持元件控制的值相关联来确定用于检测电路的状态保持操作中的缺陷的一个或多个模式故障; 并为一个或多个模式故障保存一个或多个值。

9. 发明授权

US07693676B1 Low power scan test for integrated circuits 有权
标题翻译：集成电路的低功耗扫描测试
公开(公告)号：US07693676B1
公开(公告)日：2010-04-06
申请号：US11704443
申请日：2007-02-09
申请人： Brion L. Keller , Vivek Chickermane , Sandeep Bhatia
发明人： Brion L. Keller , Vivek Chickermane , Sandeep Bhatia
IPC分类号： G01R27/28
CPC分类号： G01R31/318575
摘要： Low power design is a critical concern and metric for integrated circuits. During scan based manufacturing test, electric power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test. Excessive electric power dissipation during scan test can result in excessive voltage variations, reduced noise margins and other signal integrity issues which could invalidate the test or may lead to premature chip failure. Power dissipation during test is minimized by selecting particular values for the unused care-bits in values of the test vectors on a probabilistic basis to minimize switching, while preserving test vector quality.
摘要翻译：低功耗设计是集成电路的关键和指标。在基于扫描的制造测试中，由于芯片可能未被设计为在扫描测试期间容忍过度的切换，因此电功耗变得更加重要。扫描测试期间过大的电力消耗可能会导致过大的电压变化，降低的噪声容限和其他信号完整性问题，这可能使测试无效或可能导致芯片过早失效。通过在概率基础上选择测试向量值中未使用的关心位的特定值来最小化测试期间的功耗，同时保持测试矢量质量。

10. 发明授权

US06986090B2 Method for reducing switching activity during a scan operation with limited impact on the test coverage of an integrated circuit 失效
公开(公告)号：US06986090B2
公开(公告)日：2006-01-10
申请号：US10078876
申请日：2002-02-20
申请人： David J. Hathaway , Brion L. Keller
发明人： David J. Hathaway , Brion L. Keller
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318583
摘要： A method for reducing the switching activity during both scan-in and scan-out operations of an integrated circuit with reduced detrimental effect on test pattern effectiveness and test time is described. The method makes use of a sample set of patterns to determine the probabilities of same and opposite relationships between stimulus and result values, and uses these probabilities to determine memory element pair compatibilities. Scan chains are ordered preferentially by connecting adjacently compatible memory elements, and inversions are inserted between selected memory element pairs based on those probabilities. Unspecified stimulus bits are filled in to reduce the switching activity based on the scan chain ordering and inversions.

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