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    • 2. 发明授权
    • Method and apparatus for a randomizer for DVD video
    • 用于DVD视频的随机发生器的方法和装置
    • US06574424B1
    • 2003-06-03
    • US09344745
    • 1999-06-25
    • Kamal E. DimitriRodney J. MeansJohn E. KulakowskiDaniel J. Winarski
    • Kamal E. DimitriRodney J. MeansJohn E. KulakowskiDaniel J. Winarski
    • H04N5781
    • G11B19/02G11B27/105G11B27/3027G11B2220/235G11B2220/2562
    • A bit is provided in each Digital Video Disk memory sector header to indicate the type of information contained in the main data portion of the frame. A vector of video clips are stored on the DVD disk and the DVD drive examines the bit to determine whether to play a movie or to employ logic provided by the present invention that allows the DVD drive to determine which included video clip to play instead. The video clips may include cartoons, commercials, movie previews, etc. and the logic employed by the DVD drive allows for random or specific selections to be played at predetermined times, such as displaying a clip during the flipping process of a dual-sided DVD disk. Additionally, the method and apparatus may be applied to DVD disks to determine whether commercials are played before, after or during the movie or the movie is played commercial free.
    • 在每个数字视频磁盘存储器扇区头部中提供一位以指示包含在帧的主数据部分中的信息的类型。 视频剪辑的矢量存储在DVD盘上,DVD驱动器检查该位以确定是否播放电影或采用允许DVD驱动器确定哪个包括视频剪辑要播放的本发明提供的逻辑。 视频剪辑可以包括漫画,广告,电影预览等,并且DVD驱动器使用的逻辑允许在预定时间播放随机或特定选择,诸如在双面DVD的翻转处理期间显示剪辑 磁盘。 此外,该方法和装置可以应用于DVD盘以确定在电影之前,之后或期间是否播放商业广告,或者电影播放商业广告。
    • 4. 发明授权
    • Allocation procedures for optical disk recorders
    • 光盘刻录机的分配程序
    • US5132853A
    • 1992-07-21
    • US504529
    • 1990-04-04
    • John E. KulakowskiRodney J. Means
    • John E. KulakowskiRodney J. Means
    • G06F3/06G11B20/12G11B20/18
    • G06F3/0601G11B20/1252G11B20/1883G06F2003/0697G11B2020/1257G11B2220/20
    • A large capacity data storing disk includes a volume table of contents (VTOC) which identifies allocated ones of data storage tracks and identification of the data contents therein, indications of unallocated data storage track and an indication of which of the data storage tracks on the large capacity disk surface are unformatted. The indications may also include indications of unallocated "erased" tracks that do not contain data residuals from previous recordings. Those unallocated tracks having such erased condition in a count key data record format (CKD) require a home address record on each of the formatted tracks. The home address record may include indications of rotational position of defects to be skipped over during the recording and readback operations. A specific embodiment of the invention using a magnetooptic record medium is described.
    • 大容量数据存储盘包括容纳内容表(VTOC),其识别分配的数据存储轨道和其中的数据内容的标识,未分配的数据存储轨迹的指示和大的数据存储轨道的指示 容量磁盘表面未格式化。 指示还可以包括不包含先前记录的数据残差的未分配“擦除”轨道的指示。 在计数密钥数据记录格式(CKD)中具有这种擦除条件的那些未分配的轨道需要每个格式化的轨道上的归属地址记录。 归属地址记录可以包括在记录和回读操作期间要跳过的缺陷的旋转位置的指示。 描述了使用磁光记录介质的本发明的具体实施例。
    • 7. 发明授权
    • Logic circuitry for selection of dedicated registers
    • 用于选择专用寄存器的逻辑电路
    • US4006457A
    • 1977-02-01
    • US550338
    • 1975-02-18
    • Edward C. HepworthRodney J. MeansCharles I. Peddle
    • Edward C. HepworthRodney J. MeansCharles I. Peddle
    • G06F15/78H04Q9/00G11C17/00H04L5/00
    • G06F15/7864
    • An MOS (Metal-Oxide-Semiconductor) integrated circuit includes four dedicated registers thereon, two of which are "write only" registers having the capability of being written into, but not read from, by means of buffer circuitry for coupling a bidirectional data bus to the dedicated registers. The other two dedicated registers are "read only" registers having the capability of being read from, but not written into, by means of the buffer circuitry. The integrated circuit chip is itself addressable by means of a plurality of address conductors of an address bus coupleable to the integrated circuit chip, and the four dedicated registers within the integrated circuit chip are further addressable by means of an additional address conductor called a register select address line. A control input conductor is coupled to the integrated circuit chip and is used to control the direction of data flow of the buffer circuitry and is also used in conjunction with the register select address line to select one of four dedicated registers. This provides the advantage of reducing the number of external connections required for the integrated circuit chip, and is possible only because the registers are dedicated.
    • MOS(金属氧化物半导体)集成电路包括四个专用寄存器,其中两个是“只写入”寄存器,其具有通过用于耦合双向数据总线的缓冲电路写入但不从其读取的能力 到专用寄存器。 另外两个专用寄存器是具有通过缓冲电路读取但不写入的能力的“只读”寄存器。 集成电路芯片本身可通过可与集成电路芯片耦合的地址总线的多个地址导体来寻址,并且集成电路芯片内的四个专用寄存器可通过称为寄存器选择的附加地址指令进一步寻址 地址栏。 控制输入​​导体耦合到集成电路芯片,并用于控制缓冲电路的数据流动方向,并结合寄存器选择地址线选择四个专用寄存器之一。 这提供了减少集成电路芯片所需的外部连接数量的优点,并且可能仅仅是因为寄存器是专用的。
    • 10. 发明授权
    • Character framing circuit
    • 字符成帧电路
    • US4284953A
    • 1981-08-18
    • US48193
    • 1979-06-13
    • Edward C. HepworthRodney J. Means
    • Edward C. HepworthRodney J. Means
    • G11B20/12H04L7/04H04L25/45H03K19/28
    • H04L7/042G11B20/12H04L25/45H04L7/041
    • A digital logic circuit provides character framing for a continuous stream of synchronous serial data characters. The digital logic circuit includes a shift register arranged for serial loading and parallel unloading of the received serial data characters. The parallel unloading of a received character triggers control logic to force a control code prefix consisting of a series of logical "1"s with a trailing logical "0" into the individual shift register stages. Serial loading of the next serial data character results in successive shifts of the control code prefix through the shift register stages. Serial loading continues until the trailing logic "0" shifts into a "shift register full" stage and is detected by the control logic. Detection of a change of state in the "shift register full" stage causes parallel unloading of the received serial data character followed by another forcing of the control code prefix to reinitiate the parallel unloading sequence.
    • 数字逻辑电路为同步串行数据字符的连续流提供字符构图。 数字逻辑电路包括一个移位寄存器,用于串行加载和并行卸载所接收的串行数据字符。 接收字符的并行卸载触发控制逻辑,以强制将包含逻辑“1”的序列组成的控制码前缀带有尾随逻辑“0”到各个移位寄存器阶段。 串行加载下一个串行数据字符会导致控制码前缀通过移位寄存器阶段的连续移位。 串行加载继续,直到尾随逻辑“0”移入“移位寄存器满”阶段,并由控制逻辑检测。 检测“移位寄存器满”阶段的状态变化导致接收的串行数据字符的并行卸载,接着是强制控制码前缀来重新启动并行卸载序列。