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1. 发明申请

US20130042217A1 STRUCTURAL MIGRATION OF INTEGRATED CIRCUIT LAYOUT 失效
标题翻译：集成电路布局的结构迁移
公开(公告)号：US20130042217A1
公开(公告)日：2013-02-14
申请号：US13205186
申请日：2011-08-08
申请人： Fook-Luen HENG , Rajiv V. Joshi , Alexey Y. Lvov , Xiaoping Tang
发明人： Fook-Luen HENG , Rajiv V. Joshi , Alexey Y. Lvov , Xiaoping Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.
摘要翻译：迁移电路布局的方法和系统。使用表征原始电路的布局结构的约束子集为目标电路构建平面图布局。通过根据多个不同的缩放比例缩放平面图布局的部分，使得平面图布局的部分与多个不同的缩放比同时缩放，从而在平面图布局上使用基于形状约束的缩放。细胞被放置在由平面图布局定义的位置处。使用所有约束来生成迁移的布局，使用基于形状约束的合法化来检查平面图布局。

2. 发明授权

US08423941B2 Structural migration of integrated circuit layout 失效
标题翻译：集成电路布局的结构迁移
公开(公告)号：US08423941B2
公开(公告)日：2013-04-16
申请号：US13205186
申请日：2011-08-08
申请人： Fook-Luen Heng , Rajiv V. Joshi , Alexey Y. Lvov , Xiaoping Tang
发明人： Fook-Luen Heng , Rajiv V. Joshi , Alexey Y. Lvov , Xiaoping Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.
摘要翻译：迁移电路布局的方法和系统。使用表征原始电路的布局结构的约束子集为目标电路构建平面图布局。通过根据多个不同的缩放比例缩放平面图布局的部分，使得平面图布局的部分与多个不同的缩放比同时缩放，从而在布局图布局上使用基于形状约束的缩放。细胞被放置在由平面图布局定义的位置处。使用所有约束来生成迁移的布局，使用基于形状约束的合法化来检查平面图布局。

3. 发明授权

US08484607B1 Decomposing layout for triple patterning lithography 失效
标题翻译：三重图案平版印刷的分解布局
公开(公告)号：US08484607B1
公开(公告)日：2013-07-09
申请号：US13413288
申请日：2012-03-06
申请人： Xiaoping Tang , Xin Yuan
发明人： Xiaoping Tang , Xin Yuan
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G03F7/70466 , G06F17/5081
摘要： An approach for decomposing a layout for triple patterning lithography is described. In one embodiment, a triple patterning conflict graph is built from a layout having pattern features specified as shapes. The triple patterning conflict graph represents the shapes in the layout and coloring constraints associated with the shapes. The shapes represented by the triple patterning conflict graph are decomposed into three colors to avoid color conflict, while balancing the color density among the three colors and minimizing a number of stitches used to represent the shapes in the layout. Color conflicts in the decomposition are resolved by selectively segmenting the shapes in the decomposition that are associated with the color conflict.
摘要翻译：描述了用于分解三重图案化光刻的布局的方法。在一个实施例中，从具有指定为形状的图案特征的布局构建三重图案化图案冲突图。三重图案化冲突图表示与形状相关联的布局和着色约束中的形状。由三重图形化冲突图表示的形状被分解为三种颜色以避免颜色冲突，同时平衡三种颜色之间的颜色密度并且最小化用于表示布局中的形状的多个针迹。通过选择性地分割与颜色冲突相关联的分解中的形状来解决分解中的颜色冲突。

4. 发明申请

US20120311517A1 PARALLEL SOLVING OF LAYOUT OPTIMIZATION 失效
标题翻译：并行优化布局优化
公开(公告)号：US20120311517A1
公开(公告)日：2012-12-06
申请号：US13151413
申请日：2011-06-02
申请人： Xiaoping Tang , Michael S. Gray , Xin Yuan
发明人： Xiaoping Tang , Michael S. Gray , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068
摘要： Solutions for optimizing an integrated circuit layout for implementation in an integrated circuit are disclosed. In one embodiment, a computer-implemented method is disclosed including: obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout; partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules; determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists; creating a plurality of integer linear programming problems associated with each of the groups; determining a solution for each of the plurality of integer linear programming problems; and integrating each solution together to form a second integrated circuit layout.
摘要翻译：公开了用于优化用于在集成电路中实现的集成电路布局的解决方案。在一个实施例中，公开了一种计算机实现的方法，包括：以数学形式获得多个分层约束，所述多个层级约束限定第一集成电路布局; 根据一个或多个分区规则将多个分层约束划分成组; 确定在两个组之间是否存在边界条件，并且在存在边界条件的情况下分配两组之间的松弛或间隙; 创建与每个组相关联的多个整数线性规划问题; 确定所述多个整数线性规划问题中的每一个的解; 并将每个解决方案集成在一起以形成第二集成电路布局。

5. 发明申请

US20110265055A1 HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT 有权
标题翻译：在集成电路布局中处理两维约束
公开(公告)号：US20110265055A1
公开(公告)日：2011-10-27
申请号：US12767375
申请日：2010-04-26
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer-implemented method for handling a plurality of constraints in layout optimization for an integrated circuit (IC) layout is disclosed. In one embodiment, the method includes building a graph representing the plurality of constraints; marking two-dimensional constraints in the plurality of constraints; generating two-dimensional clusters including groups of the two-dimensional constraints; handling at least one of the two-dimensional clusters, the handling including finding a solution for the two-dimensional constraints in the at least one two-dimensional cluster; repeating the handling for any unprocessed two-dimensional clusters until all of the two-dimensional clusters are handled; and adopting the solution for each of the two-dimensional clusters to solve at least a portion of the plurality of constraints including the two-dimensional clusters.
摘要翻译：公开了一种用于处理集成电路（IC）布局的布局优化中的多个约束的计算机实现的方法。在一个实施例中，该方法包括构建表示多个约束的图; 标记所述多个约束中的二维约束; 生成包括二维约束的二维群集; 处理所述二维集群中的至少一个，所述处理包括找到所述至少一个二维集群中的二维约束的解; 重复对任何未处理的二维簇的处理，直到处理所有二维簇; 并且针对每个二维聚类采用解，以解决包括二维聚类的多个约束的至少一部分。

6. 发明申请

US20090158223A1 ADAPTIVE WEIGHTING METHOD FOR LAYOUT OPTIMIZATION WITH MULTIPLE PRIORITIES 有权
标题翻译：具有多重优先权的布局优化的自适应加权方法
公开(公告)号：US20090158223A1
公开(公告)日：2009-06-18
申请号：US11958606
申请日：2007-12-18
申请人： Michael S. Gray , Matthew T. Guzowski , Kevin W. McCullen , Xiaoping Tang , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , Matthew T. Guzowski , Kevin W. McCullen , Xiaoping Tang , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/08
摘要： An adaptive weighting method for layout optimization differentiates different priorities by assigning the weight of a higher priority (pi) to be multiple of the weight of a lower priority (pi−1) where W(pi)=mi % W(pi−1. To avoid numerical imprecision, this method keeps the total cost in the objective function within a trustable range by scaling the initial weights in the objectives, while maintaining relativity, to produce the scaled weights.
摘要翻译：用于布局优化的自适应加权方法通过将较高优先级（pi）的权重分配为较低优先级（pi-1）的权重的倍数来区分不同的优先级，其中W（pi）= mi％W（pi-1）为了避免数值不精确，该方法将目标函数中的总成本保持在可信范围内，通过缩放目标中的初始权重，同时维持相对性，以产生缩放权重。

7. 发明授权

US07305641B2 Method and system to redistribute white space for minimizing wire length 失效
标题翻译：重新分配白色空间以最小化电线长度的方法和系统
公开(公告)号：US07305641B2
公开(公告)日：2007-12-04
申请号：US11034098
申请日：2005-01-12
申请人： Xiaoping Tang
发明人： Xiaoping Tang
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： Disclosed are a method and a system for redistributing white space on an integrated circuit. The method comprises the steps of providing a series of circuit blocks for the integrated circuit, and placing the blocks on the integrated circuit to obtain a predefined optimal wire length. In accordance with the preferred embodiment of the invention, we first show that the problem of placing the blocks to obtain an optimal wire length, can be formulated as linear programming. Then, we find it can be solved by efficient min-cost flow implementation instead of general and slow linear programming. The approach guarantees to obtain the minimum total wire length for a given floorplan topology. We also show that the approach is capable of handling various constraints such as fixed-frame (fixed area), IO pins, pre-placed blocks, boundary blocks, range placement, alignment and abutment, rectilinear blocks, cluster placement, and bounded net delay, without loss of optimality.
摘要翻译：公开了一种用于在集成电路上重新分配空白空间的方法和系统。该方法包括以下步骤：为集成电路提供一系列电路块，并将块放置在集成电路上以获得预定义的最佳导线长度。根据本发明的优选实施例，我们首先示出了放置块以获得最佳线长度的问题可以被公式化为线性规划。然后，我们发现它可以通过有效的最小成本流实现而不是一般和慢线性规划来解决。该方法保证获得给定平面图拓扑的最小总线长度。我们还表明，该方法能够处理诸如固定帧（固定区域），IO引脚，预置块，边界块，范围布局，对准和邻接，直线块，簇放置和有界网络延迟等各种约束，不失最优。

8. 发明授权

US08799844B2 Layout decomposition method and apparatus for multiple patterning lithography 有权
标题翻译：布图分解方法和装置用于多重图案化光刻
公开(公告)号：US08799844B2
公开(公告)日：2014-08-05
申请号：US13016033
申请日：2011-01-28
申请人： Minsik Cho , Xiaoping Tang
发明人： Minsik Cho , Xiaoping Tang
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70475
摘要： An initial layout of at least a portion of a given layer of an integrated circuit design is decomposed into multiple sub-layouts by splitting each of a plurality of shapes of the initial layout into multiple segments, constructing a constraint graph to represent relationships between the segments, reducing the constraint graph to a stitch graph, determining at least one cut line of the stitch graph, and generating a decomposed layout based on the determined cut line. The decomposed layout in an illustrative embodiment includes first and second sub-layouts comprising respective disjoint subsets of the segments, with each of the sub-layouts of the decomposed layout being associated with a different pattern mask of a double patterning lithography process. The layout decomposition process advantageously minimizes the number of stitches between the sub-layouts without introducing excessive computational complexity.
摘要翻译：将集成电路设计的给定层的至少一部分的初始布局通过将初始布局的多个形状中的每一个划分成多个段来分解成多个子布局，构建约束图以表示段之间的关系将所述约束图减少到针迹图，确定所述针迹图的至少一个切割线，以及基于所确定的切割线来生成分解的布局。在说明性实施例中的分解布局包括包括段的相应不相交子集的第一和第二子布局，其中分解布局的每个子布局与双图案化光刻工艺的不同图案掩模相关联。布局分解过程有利地使子布局之间的线迹数目最小化，而不引入过多的计算复杂度。

9. 发明授权

US08555229B2 Parallel solving of layout optimization 失效
标题翻译：并行求解布局优化
公开(公告)号：US08555229B2
公开(公告)日：2013-10-08
申请号：US13151413
申请日：2011-06-02
申请人： Xiaoping Tang , Michael S. Gray , Xin Yuan
发明人： Xiaoping Tang , Michael S. Gray , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068
摘要： Solutions for optimizing an integrated circuit layout for implementation in an integrated circuit are disclosed. In one embodiment, a computer-implemented method is disclosed including: obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout; partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules; determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists; creating a plurality of integer linear programming problems associated with each of the groups; determining a solution for each of the plurality of integer linear programming problems; and integrating each solution together to form a second integrated circuit layout.
摘要翻译：公开了用于优化用于在集成电路中实现的集成电路布局的解决方案。在一个实施例中，公开了一种计算机实现的方法，包括：以数学形式获得多个分层约束，所述多个层级约束限定第一集成电路布局; 根据一个或多个分区规则将多个分层约束划分成组; 确定在两个组之间是否存在边界条件，并且在存在边界条件的情况下分配两组之间的松弛或间隙; 创建与每个组相关联的多个整数线性规划问题; 确定所述多个整数线性规划问题中的每一个的解; 并将每个解决方案集成在一起以形成第二集成电路布局。

10. 发明申请

US20080046854A1 METHOD AND SYSTEM TO REDISTRIBUTE WHITE SPACE FOR MINIMIZING WIRE LENGTH 有权
标题翻译：用于最小化线长的REDISTRIBUTE白色空间的方法和系统
公开(公告)号：US20080046854A1
公开(公告)日：2008-02-21
申请号：US11925238
申请日：2007-10-26
申请人： Xiaoping Tang
发明人： Xiaoping Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Disclosed are a method and a system for redistributing white space on an integrated circuit. The method comprises the steps of providing a series of circuit blocks for the integrated circuit, and placing the blocks on the integrated circuit to obtain a predefined optimal wire length. In accordance with the preferred embodiment of the invention, we first show that the problem of placing the blocks to obtain an optimal wire length, can be formulated as linear programming. Then, we find it can be solved by efficient min-cost flow implementation instead of general and slow linear programming. The approach guarantees to obtain the minimum total wire length for a given floorplan topology. We also show that the approach is capable of handling various constraints such as fixed-frame (fixed area), IO pins, pre-placed blocks, boundary blocks, range placement, alignment and abutment, rectilinear blocks, cluster placement, and bounded net delay, without loss of optimality.
摘要翻译：公开了一种用于在集成电路上重新分配空白空间的方法和系统。该方法包括以下步骤：为集成电路提供一系列电路块，并将块放置在集成电路上以获得预定义的最佳导线长度。根据本发明的优选实施例，我们首先示出了放置块以获得最佳线长度的问题可以被公式化为线性规划。然后，我们发现它可以通过有效的最小成本流实现而不是一般和慢线性规划来解决。该方法保证获得给定平面图拓扑的最小总线长度。我们还表明，该方法能够处理诸如固定帧（固定区域），IO引脚，预置块，边界块，范围布局，对准和邻接，直线块，簇放置和有界网络延迟等各种约束，不失最优。

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