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1. 发明申请

US20130007375A1 DEVICE AND METHOD FOR EXCHANGING DATA BETWEEN MEMORY CONTROLLERS 有权
公开(公告)号：US20130007375A1
公开(公告)日：2013-01-03
申请号：US13534063
申请日：2012-06-27
申请人： Florian Alexander Auernhammer , Victoria Caparros Cabezas , Andreas Christian Doering , Patricia Maria Sagmeister
发明人： Florian Alexander Auernhammer , Victoria Caparros Cabezas , Andreas Christian Doering , Patricia Maria Sagmeister
IPC分类号： G06F12/08 , G06F12/16 , G06F12/00
CPC分类号： G06F13/16 , G06F13/1657
摘要： A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.

2. 发明申请

US20130007398A1 DEVICE AND METHOD FOR EXCHANGING DATA BETWEEN MEMORY CONTROLLERS 审中-公开
标题翻译：用于在存储器控制器之间交换数据的装置和方法
公开(公告)号：US20130007398A1
公开(公告)日：2013-01-03
申请号：US13603521
申请日：2012-09-05
申请人： Florian Alexander Auernhammer , Victoria Caparros Cabezas , Andreas Christian Doering , Patricia Maria Sagmeister
发明人： Florian Alexander Auernhammer , Victoria Caparros Cabezas , Andreas Christian Doering , Patricia Maria Sagmeister
IPC分类号： G06F12/02
CPC分类号： G06F13/16 , G06F13/1657
摘要： A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.
摘要翻译：具有互连的设备，具有用于连接多个存储器控制器的多个存储器控制器。多个存储器控制器中的每个存储器控制器耦合到分配的用于存储数据的存储器。此外，多个存储器控制器的每个存储器控制器具有用于在互连上相互交换数据的多个加速器的一个加速器。

3. 发明授权

US08972667B2 Exchanging data between memory controllers 有权
标题翻译：在内存控制器之间交换数据
公开(公告)号：US08972667B2
公开(公告)日：2015-03-03
申请号：US13534063
申请日：2012-06-27
申请人： Florian Alexander Auernhammer , Victoria Caparros Cabezas , Andreas Christian Doering , Patricia Maria Sagmeister
发明人： Florian Alexander Auernhammer , Victoria Caparros Cabezas , Andreas Christian Doering , Patricia Maria Sagmeister
IPC分类号： G06F12/00 , G06F12/08 , G06F12/16 , G06F13/16
CPC分类号： G06F13/16 , G06F13/1657
摘要： A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.
摘要翻译：具有互连的设备，具有用于连接多个存储器控制器的多个存储器控制器。多个存储器控制器中的每个存储器控制器耦合到分配的用于存储数据的存储器。此外，多个存储器控制器的每个存储器控制器具有用于在互连上相互交换数据的多个加速器的一个加速器。

4. 发明授权

US07613850B1 System and method utilizing programmable ordering relation for direct memory access 有权
标题翻译：使用可编程排序关系进行直接存储器访问的系统和方法
公开(公告)号：US07613850B1
公开(公告)日：2009-11-03
申请号：US12343092
申请日：2008-12-23
申请人： Andreas Christian Doering , Patricia Maria Sagmeister , Jonathan Bruno Rohrer , Silvio Dragone , Rolf Clauberg , Florian Alexander Auernhammer , Maria Gabrani
发明人： Andreas Christian Doering , Patricia Maria Sagmeister , Jonathan Bruno Rohrer , Silvio Dragone , Rolf Clauberg , Florian Alexander Auernhammer , Maria Gabrani
IPC分类号： G06F3/00
CPC分类号： G06F13/1621
摘要： A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.
摘要翻译：计算机系统根据编程配置的排序类协议来控制有序存储器操作，以在维持有序读取响应的同时启用并行存储器访问。该系统包括存储器和/或高速缓存存储器，其包括存储器/高速缓存控制器，用于从系统数据源传送存储器访问请求的I / O设备和存储器控制器I / O接口。来自系统数据源的存储器访问请求提供了相应的排序类值。存储器控制器I / O接口根据排序类协议处理从数据源通过I / O设备传送的每个存储器访问请求和排序类值。优选地，I / O设备包括至少一个用于存储与实现存储器访问请求的系统数据源相关联的排序类值的寄存器。

5. 发明授权

US08772877B2 Tunnel field-effect transistor 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US08772877B2
公开(公告)日：2014-07-08
申请号：US13551785
申请日：2012-07-18
申请人： Mikael T Bjoerk , Andreas Christian Doering , Phillip Stanley-Marbell , Kirsten Emilie Moselund
发明人： Mikael T Bjoerk , Andreas Christian Doering , Phillip Stanley-Marbell , Kirsten Emilie Moselund
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/42312
摘要： A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region.
摘要翻译：一种隧道场效应晶体管，至少包括：包括相应源极半导体材料的源区; 包括相应的漏极半导体材料的漏极区域和布置在源极区域和漏极区域之间的包括相应的沟道半导体材料的沟道区域。隧道场效应晶体管至少还包括：设置在源极区域和沟道区域之间的界面上的源极沟道栅电极; 与源极栅极电极和源极区域与沟道区域之间的界面之间设置的与源极栅极电极对应的绝缘体; 漏极沟道栅电极，设置在漏区和沟道区之间的界面上; 以及设置在漏极沟道栅电极和漏极区域与沟道区域之间的界面之间的与漏极沟道栅电极相对应的绝缘体。

6. 发明申请

US20120054450A1 BALANCING LOADS OF A PLURALTY OF BUS LANES OF A SNOOPING-BASED BUS 失效
标题翻译：基于SNOOPING的总线的总线的平衡负载平衡
公开(公告)号：US20120054450A1
公开(公告)日：2012-03-01
申请号：US13221051
申请日：2011-08-30
申请人： Andreas Christian Doering
发明人： Andreas Christian Doering
IPC分类号： G06F12/08
CPC分类号： G06F13/4204
摘要： A method and system for balancing loads of a plurality of bus lanes of a snooping-based bus. The system includes: a receiver for receiving snoop transactions from the bus lanes, each of the snoop transactions having a snoop request and at least one snoop response, an analyzer for analyzing respective actual and expected loads of each of the bus lanes dependent on the received snoop transactions, and a controller for providing a next snoop request from a number of outstanding snoop requests to a buffer allocated to the system, where the buffer is dependent on the analyzed loads of the bus lanes.
摘要翻译：一种用于平衡基于窥探的总线的多个总线通道的负载的方法和系统。该系统包括：用于从总线通道接收窥探事务的接收器，每个窥探事务具有窥探请求和至少一个侦听响应;分析器，用于分析取决于所接收的每个总线通道的各个实际和预期的负载监听事务，以及控制器，用于从分配给系统的缓冲区中提供来自多个未完成侦听请求的下一个窥探请求，其中缓冲区取决于分析的总线通道的负载。

7. 发明授权

US08677041B2 Balancing loads of a plurality of bus lanes of a snooping-based bus using a receiver, analyzer, and controller 失效
标题翻译：使用接收器，分析仪和控制器平衡基于窥探的总线的多个总线通道的负载
公开(公告)号：US08677041B2
公开(公告)日：2014-03-18
申请号：US13221051
申请日：2011-08-30
申请人： Andreas Christian Doering
发明人： Andreas Christian Doering
IPC分类号： G06F12/00
CPC分类号： G06F13/4204
摘要： A method and system for balancing loads of a plurality of bus lanes of a snooping-based bus. The system includes: a receiver for receiving snoop transactions from the bus lanes, each of the snoop transactions having a snoop request and at least one snoop response, an analyzer for analyzing respective actual and expected loads of each of the bus lanes dependent on the received snoop transactions, and a controller for providing a next snoop request from a number of outstanding snoop requests to a buffer allocated to the system, where the buffer is dependent on the analyzed loads of the bus lanes.
摘要翻译：一种用于平衡基于窥探的总线的多个总线通道的负载的方法和系统。该系统包括：用于从总线通道接收窥探事务的接收器，每个窥探事务具有窥探请求和至少一个侦听响应;分析器，用于分析取决于所接收到的每个总线通道的各个实际和预期负载监听事务，以及控制器，用于从分配给系统的缓冲区中提供来自多个未完成侦听请求的下一个窥探请求，其中缓冲区取决于分析的总线通道的负载。

8. 发明申请

US20130021061A1 TUNNEL FIELD-EFFECT TRANSISTOR 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US20130021061A1
公开(公告)日：2013-01-24
申请号：US13551785
申请日：2012-07-18
申请人： Mikael T. Bjoerk , Andreas Christian Doering , Phillip Stanley-Marbell , Kirsten Emilie Moselund
发明人： Mikael T. Bjoerk , Andreas Christian Doering , Phillip Stanley-Marbell , Kirsten Emilie Moselund
IPC分类号： H01L29/78 , H03K19/21 , H01L21/336
CPC分类号： H01L29/7391 , H01L29/42312
摘要： A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region.
摘要翻译：一种隧道场效应晶体管，至少包括：包括相应源极半导体材料的源区; 包括相应的漏极半导体材料的漏极区域和布置在源极区域和漏极区域之间的包括相应的沟道半导体材料的沟道区域。隧道场效应晶体管至少还包括：设置在源极区域和沟道区域之间的界面上的源极沟道栅电极; 与源极栅极电极和源极区域与沟道区域之间的界面之间设置的与源极栅极电极对应的绝缘体; 漏极沟道栅电极，设置在漏区和沟道区之间的界面上; 以及设置在漏极沟道栅电极和漏极区域与沟道区域之间的界面之间的与漏极沟道栅电极相对应的绝缘体。

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