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1. 发明授权

US08234603B2 Method for fast estimation of lithographic binding patterns in an integrated circuit layout 有权
标题翻译：用于在集成电路布局中快速估计光刻结合图案的方法
公开(公告)号：US08234603B2
公开(公告)日：2012-07-31
申请号：US12835891
申请日：2010-07-14
申请人： Saeed Bagheri , David L. DeMaris , Maria Gabrani , David Osmond Melville , Alan E. Rosenbluth , Kehan Tian
发明人： Saeed Bagheri , David L. DeMaris , Maria Gabrani , David Osmond Melville , Alan E. Rosenbluth , Kehan Tian
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G06F17/5081
摘要： The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate θi of spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate θi, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate θi, and a total energy entropy factor comprising total energy entropy of said diffraction orders. The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1. The value of the lithographic difficulty metric may be used to identify patterns in a design layout that are binding patterns in an optimization computation. The lithographic difficulty metric may be used to design integrated circuits that have good, relatively easy-to-print characteristics.
摘要翻译：本发明提供了一种光刻难度度量，其是能量比因子的函数，能量比因子包括沿着角坐标和空间频率空间的角度i的衍射级的难以打印能量的容易打印能量的比率包括沿着所述角坐标和所述角度坐标的所述衍射级的能量熵的能量熵因子; i，包括所述衍射级沿着所述角坐标系的所述衍射级的相位熵的相位熵因子; i，以及包括总能量熵的总能量熵因子说衍射订单。难以打印的能量包括在r = 0和r = 1附近的空间频率空间的归一化径向坐标r的值的衍射级的能量，并且易于打印的能量包括位于r = 0的邻域和r = 1附近的归一化的径向坐标r的中间值处的衍射级的能量。光刻难度度量的值可用于识别在优化计算中的结合模式的设计布局中的图案。光刻难度度可用于设计具有良好，相对易于打印的特性的集成电路。

2. 发明授权

US07058951B2 Method and a system for allocation of a budget to a task 有权
标题翻译：方法和为任务分配预算的系统
公开(公告)号：US07058951B2
公开(公告)日：2006-06-06
申请号：US10169346
申请日：2001-11-02
申请人： Reinder Jaap Bril , Elisabeth Francisca Maria Steffens , Christian Hentschel , Maria Gabrani , Cornelis Conradus Adrianus Maria Van Zon
发明人： Reinder Jaap Bril , Elisabeth Francisca Maria Steffens , Christian Hentschel , Maria Gabrani , Cornelis Conradus Adrianus Maria Van Zon
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： In consumer devices, like digital television sets or set-top boxes, there can be a problem with a sudden load increase caused by for example a scene change and user focus. During such a load increase, the quality of service of the application having the user focus will decrease until the device detects the load increase. The device can reallocate resources to the application having the user focus after which the quality of service will increase again towards its previous level. However, the user may have noticed the quality decrease. In order to prevent this noticeable decrease of quality in overload situations, a method and a system are provided that guarantees a worst-case budget to the application having user focus and conditionally guarantees a budget surplus to an application not having the user focus. The latter application can then use that budget surplus to operate at a higher quality of service level.
摘要翻译：在诸如数字电视机或机顶盒的消费者设备中，由于例如场景改变和用户焦点引起的突然的负载增加可能存在问题。在这样的负载增加期间，具有用户聚焦的应用的服务质量将降低，直到设备检测到负载增加。该设备可以将资源重新分配给具有用户焦点的应用，之后服务质量将再次增加到其先前的水平。然而，用户可能已经注意到质量下降。为了防止在过载情况下质量明显下降，提供了一种方法和系统，其保证对具有用户重点的应用的最坏情况预算，并有条件地保证对不具有用户焦点的应用的预算盈余。后一种应用可以使用这种预算盈余在更高的服务质量水平上运行。

3. 发明授权

US08363922B2 IC layout pattern matching and classification system and method 失效
标题翻译： IC布局模式匹配与分类系统及方法
公开(公告)号：US08363922B2
公开(公告)日：2013-01-29
申请号：US12370102
申请日：2009-02-12
申请人： Maria Gabrani , Paul Hurley
发明人： Maria Gabrani , Paul Hurley
IPC分类号： G06K9/00 , G06K9/46
CPC分类号： G06F17/5081 , G06K9/00476 , G06K9/0055
摘要： A system and method for restricting the number of layout patterns by pattern identification, matching and classification, includes decomposing the pattern windows into a low frequency component and a high frequency component using a wavelet analysis for an integrated circuit layout having a plurality of pattern windows. Using the low frequency component as an approximation, a plurality of moments is computed for each pattern window. The pattern windows are classified using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows.
摘要翻译：通过图案识别，匹配和分类来限制布局图案的数量的系统和方法包括使用具有多个图案窗口的集成电路布局的小波分析将图案窗口分解为低频分量和高频分量。使用低频分量作为近似，为每个模式窗口计算多个力矩。通过将距离计算与误差值进行比较来确定图案窗口之间的相似度，对图案窗口的各个时刻的距离计算进行分类。

4. 发明授权

US07613850B1 System and method utilizing programmable ordering relation for direct memory access 有权
标题翻译：使用可编程排序关系进行直接存储器访问的系统和方法
公开(公告)号：US07613850B1
公开(公告)日：2009-11-03
申请号：US12343092
申请日：2008-12-23
申请人： Andreas Christian Doering , Patricia Maria Sagmeister , Jonathan Bruno Rohrer , Silvio Dragone , Rolf Clauberg , Florian Alexander Auernhammer , Maria Gabrani
发明人： Andreas Christian Doering , Patricia Maria Sagmeister , Jonathan Bruno Rohrer , Silvio Dragone , Rolf Clauberg , Florian Alexander Auernhammer , Maria Gabrani
IPC分类号： G06F3/00
CPC分类号： G06F13/1621
摘要： A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.
摘要翻译：计算机系统根据编程配置的排序类协议来控制有序存储器操作，以在维持有序读取响应的同时启用并行存储器访问。该系统包括存储器和/或高速缓存存储器，其包括存储器/高速缓存控制器，用于从系统数据源传送存储器访问请求的I / O设备和存储器控制器I / O接口。来自系统数据源的存储器访问请求提供了相应的排序类值。存储器控制器I / O接口根据排序类协议处理从数据源通过I / O设备传送的每个存储器访问请求和排序类值。优选地，I / O设备包括至少一个用于存储与实现存储器访问请求的系统数据源相关联的排序类值的寄存器。

5. 发明申请

US20120017194A1 METHOD FOR FAST ESTIMATION OF LITHOGRAPHIC BINDING PATTERNS IN AN INTEGRATED CIRCUIT LAYOUT 有权
标题翻译：用于快速估计集成电路布局中的平面结合图案的方法
公开(公告)号：US20120017194A1
公开(公告)日：2012-01-19
申请号：US12835891
申请日：2010-07-14
申请人： Saeed Bagheri , David L. DeMaris , Maria Gabrani , David Osmond Melville , Alan E. Rosenbluth , Kehan Tian
发明人： Saeed Bagheri , David L. DeMaris , Maria Gabrani , David Osmond Melville , Alan E. Rosenbluth , Kehan Tian
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G03F1/70 , G06F17/5081
摘要： The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate θi spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate θi, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate θi, and a total energy entropy factor comprising total energy entropy of said diffraction orders. The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1. The value of the lithographic difficulty metric may be used to identify patterns in a design layout that are binding patterns in an optimization computation. The lithographic difficulty metric may be used to design integrated circuits that have good, relatively easy-to-print characteristics.
摘要翻译：本发明提供了一种光刻难度度量，其是能量比因子的函数，能量比因子包括沿着角坐标系的衍射级的难以打印能量与易于打印能量的比率; i空间频率空间，包括沿着所述角坐标和所述衍射级的能量熵的能量熵因子; i，包括所述衍射级沿着所述角坐标和所述角度的所述衍射级的相位熵的相位熵因子; i，以及包括所述总体能量熵的总能量熵因子衍射指令。难以打印的能量包括在r = 0和r = 1附近的空间频率空间的归一化径向坐标r的值的衍射级的能量，并且易于打印的能量包括位于r = 0的邻域和r = 1附近的归一化的径向坐标r的中间值处的衍射级的能量。光刻难度度量的值可用于识别在优化计算中的结合模式的设计布局中的图案。光刻难度度可用于设计具有良好的，相对易于打印的特性的集成电路。

6. 发明授权

US07990869B2 Method for monitoring data congestion in a computer network with multiple nodes and method for controlling data transmission in the computer network 有权
标题翻译：用于监控具有多个节点的计算机网络中的数据拥塞的方法和用于控制计算机网络中的数据传输的方法
公开(公告)号：US07990869B2
公开(公告)日：2011-08-02
申请号：US12323514
申请日：2008-11-26
申请人： Wolfgang Emil Denzel , Andreas Christian Döring , Maria Gabrani , Mircea Gusat , Patricia Maria Sagmeister , Thomas Schlipf
发明人： Wolfgang Emil Denzel , Andreas Christian Döring , Maria Gabrani , Mircea Gusat , Patricia Maria Sagmeister , Thomas Schlipf
IPC分类号： H04L12/26 , H04L12/28
CPC分类号： H04L47/10 , H04L43/0882 , H04L43/16 , H04L47/115 , H04L47/26 , H04L47/32
摘要： A method for monitoring data congestion in a computer network with multiple nodes and for controlling data transmission in the computer network. The method includes generating a congestion notification by the node which detects a data congestion and transmitting the congestion notification to the data source which is involved in the data congestion. The method also includes generating in the data source a congestion value which indicates how severe the data congestion is, and storing in a worst case array of the data source those congestion values which indicate the most severe data congestions.
摘要翻译：一种用于监视具有多个节点的计算机网络中的数据拥塞并用于控制计算机网络中的数据传输的方法。该方法包括：通过检测数据拥塞的节点生成拥塞通知，并将拥塞通知发送到参与数据拥塞的数据源。该方法还包括在数据源中产生表示数据拥塞程度如何严重的拥塞值，以及在数据源的最坏情况阵列中存储指示最严重数据拥塞的拥塞值。

7. 发明申请

US20100202706A1 IC LAYOUT PATTERN MATCHING AND CLASSIFICATION SYSTEM AND METHOD 失效
标题翻译： IC布局图案匹配和分类系统及方法
公开(公告)号：US20100202706A1
公开(公告)日：2010-08-12
申请号：US12370102
申请日：2009-02-12
申请人： Maria Gabrani , Paul Hurley
发明人： Maria Gabrani , Paul Hurley
IPC分类号： G06K9/62
CPC分类号： G06F17/5081 , G06K9/00476 , G06K9/0055
摘要： A system and method for restricting the number of layout patterns by pattern identification, matching and classification, includes decomposing the pattern windows into a low frequency component and a high frequency component using a wavelet analysis for an integrated circuit layout having a plurality of pattern windows. Using the low frequency component as an approximation, a plurality of moments is computed for each pattern window. The pattern windows are classified using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows.
摘要翻译：通过图案识别，匹配和分类来限制布局图案的数量的系统和方法包括使用具有多个图案窗口的集成电路布局的小波分析将图案窗口分解为低频分量和高频分量。使用低频分量作为近似，为每个模式窗口计算多个力矩。通过将距离计算与误差值进行比较来确定图案窗口之间的相似度，对图案窗口的各个时刻的距离计算进行分类。

8. 发明申请

US20050125797A1 Resource management for a system-on-chip (SoC) 审中-公开
标题翻译：片上系统（SoC）的资源管理
公开(公告)号：US20050125797A1
公开(公告)日：2005-06-09
申请号：US11005955
申请日：2004-12-07
申请人： Maria Gabrani , Andreas Doering , Patricia Saqmeister , Peter Buchmann , Andreas Herkersdorf
发明人： Maria Gabrani , Andreas Doering , Patricia Saqmeister , Peter Buchmann , Andreas Herkersdorf
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F2209/5019 , G06F2209/5022
摘要： Provides evaluation and management of system resources in a data processing system, particularly in a SoC device and for optimizing the operation of the system wherein the system having a plurality of components each operable to process dedicated tasks in the data processing system, wherein each of the components has its associated current resource usages depending on the currently processed task and/or its future resource usage depending on the tasks to be processed next, wherein the resource usage indicates the type of resources and the amount of resources used, wherein the processing of the task of at least one of the components can be modified to adapt the resource usage of this or other component. A method including: determining operating states; estimating current and future resource usage; if necessary adapting task processing according to a predefined scheme to reduce the-resource usage.
摘要翻译：提供在数据处理系统中的系统资源的评估和管理，特别是在SoC设备中并用于优化系统的操作的系统资源，其中系统具有多个组件，每个组件可操作以处理数据处理系统中的专用任务，其中组件具有取决于当前处理的任务和/或其将来的资源使用的相关联的当前资源使用，这取决于接下来要处理的任务，其中资源使用指示资源的类型和所使用的资源的数量，其中处理可以修改至少一个组件的任务以适应该组件或其他组件的资源使用。一种方法，包括：确定运行状态; 估计当前和未来的资源使用情况; 如果必要，根据预定义的方案适应任务处理以减少资源使用。

9. 发明授权

US08667427B2 Method of optimization of a manufacturing process of an integrated circuit layout 失效
标题翻译：集成电路布局制造工艺优化方法
公开(公告)号：US08667427B2
公开(公告)日：2014-03-04
申请号：US13402941
申请日：2012-02-23
申请人： David L. DeMaris , Maria Gabrani , Ekaterina Volkova
发明人： David L. DeMaris , Maria Gabrani , Ekaterina Volkova
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F7/70125 , G03F7/705
摘要： A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.
摘要翻译：计算机实现的方法，制造品和用于优化集成电路或IC布局的制造过程的计算机系统。该方法包括：接收输入; 组织IC模式; 在有组织的IC模式中选择IC模式; 并且基于所选择的IC图案优化IC布局的制造过程的设计。

10. 发明申请

US20120324406A1 METHOD OF OPTIMIZATION OF A MANUFACTURING PROCESS OF AN INTEGRATED CIRCUIT LAYOUT 有权
公开(公告)号：US20120324406A1
公开(公告)日：2012-12-20
申请号：US13594198
申请日：2012-08-24
申请人： David L. DeMaris , Maria Gabrani , Ekaterina Volkova
发明人： David L. DeMaris , Maria Gabrani , Ekaterina Volkova
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F7/70125 , G03F7/705
摘要： A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.

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