专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4672235A Bipolar power transistor 失效
标题翻译：双极功率晶体管
公开(公告)号：US4672235A
公开(公告)日：1987-06-09
申请号：US736810
申请日：1985-05-21
申请人： Flavio Villa , Bruno Murari , Carlo Cini , Franco Bertotti
发明人： Flavio Villa , Bruno Murari , Carlo Cini , Franco Bertotti
IPC分类号： H01L29/73 , H01L21/331 , H03F3/21 , H03K17/60
CPC分类号： H03F3/211
摘要： A power transistor comprising a plurality of elementary transistors coupled in parallel and an identical number of current generators, each of which has a terminal coupled individually to the base of an elementary transistor is described. High power levels may be achieved with a transistor of this type without forward secondary breakdown taking place.
摘要翻译：描述了并联耦合的多个基本晶体管和相同数量的电流发生器的功率晶体管，每个电流发生器具有分别耦合到基本晶体管的基极的端子。这种类型的晶体管可以实现高功率电平，而不会发生正向二次击穿。

2. 发明授权

US4682197A Power transistor with spaced subtransistors having individual collectors 失效
标题翻译：具有间隔子晶体管的功率晶体管具有各自的收集器
公开(公告)号：US4682197A
公开(公告)日：1987-07-21
申请号：US812109
申请日：1985-12-23
申请人： Flavio Villa , Bruno Murari , Franco Bertotti , Aldo Torazzina , Fabrizio Stefani
发明人： Flavio Villa , Bruno Murari , Franco Bertotti , Aldo Torazzina , Fabrizio Stefani
IPC分类号： H01L21/8222 , H01L21/331 , H01L27/02 , H01L27/06 , H01L27/082 , H01L27/102 , H01L29/73 , H01L29/72 , H01L23/52 , H01L27/10 , H01L29/08
CPC分类号： H01L27/0211 , H01L27/1024
摘要： This integrated semiconductor device aims at drastic reduction of the direct secondary breakdown phenomena and has a plurality of side-by-side elementary transistors forming an interdigited structure. To reduce the thermal interaction between the elementary transistors, the latter are spaced apart from one another by a distance approximately equal to the width of one elementary transistor and are driven by current sources. Spacing apart reduces electrothermal interaction. Further, in order to minimize the device area requirements, the space between any two adjacent elementary transistors is made to accommodate drive transistors operating as current sources, or the elementary transistors of the complementary stage where the device forms a class B output stage, the two output transistors whereof are alternatively switched on.
摘要翻译：该集成半导体器件旨在大大减少直接二次击穿现象，并且具有形成交叉结构的多个并排基本晶体管。为了减小基本晶体管之间的热相互作用，后者彼此间隔开大约等于一个基本晶体管的宽度的距离，并由电流源驱动。间距减少电热相互作用。此外，为了最小化器件面积要求，使任何两个相邻基本晶体管之间的空间适合作为电流源工作的驱动晶体管，或者是器件形成B类输出级的补充级的基本晶体管，输出晶体管交替接通。

3. 发明授权

US4887142A Monolithically integrated semiconductor device containing bipolar junction transistors, CMOS and DMOS transistors and low leakage diodes and a method for its fabrication 失效
标题翻译：包含双极结晶体管，CMOS和DMOS晶体管和低漏极二极管的单片集成半导体器件及其制造方法
公开(公告)号：US4887142A
公开(公告)日：1989-12-12
申请号：US276890
申请日：1988-11-28
申请人： Franco Bertotti , Carlo Cini , Claudio Contiero , Paola Galbiati
发明人： Franco Bertotti , Carlo Cini , Claudio Contiero , Paola Galbiati
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249 , H01L27/0623
摘要： Disclosed is a monolithic integrated semiconductor device which may contain specimens of seven different circuit components; namely: lateral N-MOS and lateral P-MOS transistors (CMOS), vertical N-DMOS and vertical P-DMOS transistors, vertical NPN bipolar transistors, vertical PNP bipolar transistors with isolated collector and low leakage junction diodes as well as a process for fabricating such a device.
摘要翻译：公开了一种单片集成半导体器件，其可以包含七个不同电路部件的样本; 即：横向N-MOS和横向P-MOS晶体管（CMOS），垂直N-DMOS和垂直P-DMOS晶体管，垂直NPN双极晶体管，具有隔离集电极和低漏极结二极管的垂直PNP双极晶体管以及用于制造这样的装置。

4. 发明授权

US4663647A Buried-resistance semiconductor device and fabrication process 失效
标题翻译：埋电阻半导体器件及制造工艺
公开(公告)号：US4663647A
公开(公告)日：1987-05-05
申请号：US779091
申请日：1985-09-23
申请人： Franco Bertotti , Paolo Ferrari , Luigi Silvestri , Flavio Villa
发明人： Franco Bertotti , Paolo Ferrari , Luigi Silvestri , Flavio Villa
IPC分类号： H01L27/04 , H01L21/761 , H01L21/822 , H01L29/8605 , H01L27/02 , H01C1/012
CPC分类号： H01L29/8605 , H01L21/761
摘要： A buried-resistance semiconductor device is constructed by forming a P-type monocrystalline silicon substrate on which an epitaxial layer of silicon doped with type N impurities is grown, a portion of the epitaxial layer being insulated by a P-type insulating region extending from the substrate to the surface of the epitaxial layer. Two suitably-spaced terminals are secured to the surface of the epitaxial layer in the area bounded by the insulating region. Two separation regions extending into the surface layer are formed in the part of the epitaxial layer between the terminals, and a buried region extends from the substrate between the separation regions without being in contact with them. The three regions are of P-type material, and have an elongated shape and are bounded at the ends by the insulating region.
摘要翻译：掩埋电阻半导体器件通过形成P型单晶硅衬底而构成，其上生长掺杂有N型杂质的硅的外延层，外延层的一部分由从P型绝缘区延伸的P型绝缘区绝缘衬底到外延层的表面。两个适当间隔的端子在由绝缘区域限定的区域中固定到外延层的表面。延伸到表面层的两个分离区域形成在端子之间的外延层的部分中，并且掩埋区域在分离区域之间从衬底延伸而不与它们接触。这三个区域是P型材料，并且具有细长形状并且在末端被绝缘区限定。

5. 发明授权

US06236225B1 Method of testing the gate oxide in integrated DMOS power transistors and integrated device comprising a DMOS power transistor 失效
标题翻译：测试集成DMOS功率晶体管中的栅极氧化物的方法和包括DMOS功率晶体管的集成器件
公开(公告)号：US06236225B1
公开(公告)日：2001-05-22
申请号：US09053881
申请日：1998-04-01
申请人： Franco Bertotti , Bruno Murari , Enrico Novarini
发明人： Franco Bertotti , Bruno Murari , Enrico Novarini
IPC分类号： G01R3126
CPC分类号： G01R31/2621
摘要： A method of testing a DMOS power transistor that includes arranging a switch between low-voltage circuitry and the gate terminal of the DMOS power transistor, maintaining the switch in an open condition, applying a stress voltage to the gate terminal, testing the functionality of the DMOS power transistor, and, if the test has a positive outcome, short-circuiting the switch through zapping by fusing a normally-open fusible link. An integrated circuit device with DMOS transistor is provided that includes a gate terminal of the DMOS transistor coupled to a control element, a normally-open switch element coupled in series between the gate terminal and the control element and including two metallic regions with an insulating between them connected in parallel with the switch element and in series between the gate terminal and the control element.
摘要翻译：一种测试DMOS功率晶体管的方法，包括在低压电路和DMOS功率晶体管的栅极端之间布置开关，将开关保持在开启状态，向栅极端施加应力电压，测试 DMOS功率晶体管，如果测试有正面的结果，可以通过熔断常开的易熔断路使开关短路。提供具有DMOS晶体管的集成电路器件，其包括耦合到控制元件的DMOS晶体管的栅极端子，串联耦合在栅极端子和控制元件之间的常开开关元件，并且包括两个金属区域之间具有绝缘它们与开关元件并联并串联连接在栅极端子和控制元件之间。

6. 发明授权

US5021860A Integrated device for shielding the injection of charges into the substrate 失效
标题翻译：用于屏蔽电荷注入衬底的集成器件
公开(公告)号：US5021860A
公开(公告)日：1991-06-04
申请号：US256008
申请日：1988-10-11
申请人： Franco Bertotti , Paolo Ferrari , Maria T. Gatti
发明人： Franco Bertotti , Paolo Ferrari , Maria T. Gatti
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/02 , H01L27/06 , H01L29/732
CPC分类号： H01L27/0248
摘要： The device for shielding the electrons injected towards the substrate by an epitaxial pocket which reaches a negative voltage with respect to said substrate, comprises a debiasing transistor arranged in reverse configuration (with collector and emitter swapped) in the same epitaxial pocket reaching a negative voltage. The transistor is connected with its emitter and its collector between the buried layer of the pocket reaching a negative voltage and the substrate, so as to debias the junction formed by the buried layer and the substrate.
摘要翻译：用于屏蔽通过相对于所述衬底达到负电压的外延袋朝向衬底注入的电子的装置包括以相反的外形槽（在集电极和发射极互换的位置）排列的去偶晶体管，该相位外延腔中的去耦晶体管达到负电压。晶体管与其发射极连接，并且其集电极连接到凹穴的掩埋层之间，达到负电压和衬底，从而使由掩埋层和衬底形成的结脱落。

7. 发明授权

US4739378A Protection of integrated circuits from electric discharge 失效
标题翻译：保护集成电路免受放电
公开(公告)号：US4739378A
公开(公告)日：1988-04-19
申请号：US15650
申请日：1987-02-17
申请人： Paolo Ferrari , Franco Bertotti
发明人： Paolo Ferrari , Franco Bertotti
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L29/90
CPC分类号： H01L27/0248
摘要： Described is an integrated semiconductor structure for the protection from electrical discharges of electrostatic origin of particularly sensitive components of an integrated circuit. The structure is almost entirely formed directly underneath a particular input pad thus requiring a minimum useful area and is characterized by very high damaging voltage and speed of intervention because of the extremely low series resistance of the two zener junctions constituting the structure.
摘要翻译：描述了用于保护集成电路的特别敏感部件的静电源的放电的集成半导体结构。该结构几乎完全由特定的输入焊盘直接形成，因此需要最小的有用面积，其特征在于非常高的损坏电压和干预速度，因为构成结构的两个齐纳结的串联电阻极低。

8. 发明授权

US4266233A I-C Wafer incorporating junction-type field-effect transistor 失效
标题翻译： I-C晶片结合结型场效应晶体管
公开(公告)号：US4266233A
公开(公告)日：1981-05-05
申请号：US103423
申请日：1979-12-14
申请人： Franco Bertotti , Mario Foroni
发明人： Franco Bertotti , Mario Foroni
IPC分类号： H01L29/78 , H01L21/76 , H01L21/761 , H01L27/06 , H01L27/088 , H01L29/808 , H01L29/80
CPC分类号： H01L21/761 , H01L27/0623 , H01L29/8083
摘要： A silicon wafer incorporating several semiconductor components, among them a junction-type field-effect transistor (J-FET) of low pinch-off voltage connectable as a resistor, comprises a substrate of P-type conductivity with an insular layer of N.sup.+ conductivity penetrated by one or more enclaves of substrate material. Thereafter, a stratum of N-doped silicon is epitaxially grown on the substrate, with formation of rising zones above each enclave and around the buried N.sup.+ layer which are heavily doped with P-type impurities to act as source connections or sinkers for an FET channel formed by the enclave or enclaves and as a barrier junction surrounding a section of the N-doped stratum which becomes the gate of the FET while the substrate serves as the drain.
摘要翻译：包含几个半导体部件的硅晶片，其中可连接为电阻器的低截止电压的结型场效应晶体管（J-FET）包括P型导电性的衬底，其具有穿透N +电导率的岛状层由一个或多个基底材料的飞行器。此后，在衬底上外延生长N掺杂硅层，在每个覆盖层周围形成上升区域，并在掩埋N +层周围形成重掺杂P型杂质的FET，用作FET沟道的源极连接或沉降片由所述飞行器或飞行器形成，并且当所述基板用作所述漏极时，所述阻挡结围绕成为所述FET的栅极的所述N掺杂层的一部分。

9. 发明授权

US4829344A Electronic semiconductor device for protecting integrated circuits against electrostatic discharges 失效
标题翻译：用于保护集成电路免受静电放电的电子半导体器件
公开(公告)号：US4829344A
公开(公告)日：1989-05-09
申请号：US921071
申请日：1986-10-20
申请人： Franco Bertotti , Paolo Ferrari
发明人： Franco Bertotti , Paolo Ferrari
IPC分类号： H01L27/06 , H01L27/02
CPC分类号： H01L27/0248
摘要： This electronic semiconductor device for protecting integrated circuits against electrostatic discharges has a minimal bulk, can withstand high damaging voltages and be produced during the same production phases as the integrated circuit to be protected. The device comprises a pair of diodes connected back to back, arranged between an input of the integrated circuit to be protected and the ground line, with the cathodes connected together and formed by a single semiconductor layer and the anodes formed in a single process phase by employing top-bottom production techniques.
摘要翻译：用于保护集成电路免受静电放电的该电子半导体器件具有最小的体积，可以承受高的损坏电压并且在与待保护的集成电路相同的生产阶段期间产生。该装置包括背对背连接的一对二极管，其布置在要被保护的集成电路的输入端和接地线之间，阴极连接在一起并由单个半导体层形成，并且阳极由单个工艺阶段形成采用顶级生产技术。

10. 发明授权

US4725810A Method of making an implanted resistor, and resistor obtained thereby 失效
标题翻译：制造注入电阻器的方法和由此获得的电阻器
公开(公告)号：US4725810A
公开(公告)日：1988-02-16
申请号：US876964
申请日：1986-06-20
申请人： Mario Foroni , Paolo Ferrari , Franco Bertotti
发明人： Mario Foroni , Paolo Ferrari , Franco Bertotti
IPC分类号： H01L27/04 , H01C17/06 , H01L21/265 , H01L21/822 , H01L29/8605 , H01C1/02 , H01C17/00 , B05D5/12 , B44C1/22
CPC分类号： H01L29/8605 , H01L21/26513 , Y10T29/49082
摘要： This method of making an implanted resistor comprises the steps of implanting the resistor with ordinary techniques and deposition over the implanted resistor of a polysilicon layer having a set thickness and fully covering the resistor. Thus, the resulting resistor is unaffected by any subsequent thermal treatments and its value remains constant irrespective of any high potential metal layers or connections crossing it. The method affords in particular resistive values of the order of 1 kOhms/square.
摘要翻译：制造注入电阻器的这种方法包括以下步骤：通过普通技术注入电阻器并沉积在具有设定厚度并完全覆盖电阻器的多晶硅层的注入电阻器上。因此，所得到的电阻器不受任何后续热处理的影响，并且其值保持恒定，而与任何高电势金属层或穿过其的连接无关。该方法特别提供约1千欧姆/平方的电阻值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式