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    • 1. 发明申请
    • Nanotip electrode non-volatile memory resistor cell
    • 纳米电极非易失性存储电阻单元
    • US20070167008A1
    • 2007-07-19
    • US11717818
    • 2007-03-14
    • Sheng HsuFengyan ZhangGregory SteckerRobert Barrowcliff
    • Sheng HsuFengyan ZhangGregory SteckerRobert Barrowcliff
    • H01L21/44
    • H01L27/101H01L45/04H01L45/1233H01L45/1273H01L45/147H01L45/16H01L45/1675
    • A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.
    • 提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。 该方法包括:形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极,其中所述存储电阻材料置于所述第一和第二电极之间。 通常,纳米针是氧化铱(IrOx),并且具有约50纳米或更小的尖端基底尺寸,在5至50nm范围内的尖端高度,以及每平方微米大于100纳米尖端的纳米密度密度。 一方面,衬底材料可以是硅,氧化硅,氮化硅或贵金属。 使用金属有机化学气相沉积(MOCVD)工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。
    • 2. 发明申请
    • Silicon phosphor electroluminescence device with nanotip electrode
    • 具有纳米尖电极的硅荧光体电致发光器件
    • US20060180817A1
    • 2006-08-17
    • US11061946
    • 2005-02-17
    • Sheng HsuFengyan ZhangGregory SteckerRobert Barrowcliff
    • Sheng HsuFengyan ZhangGregory SteckerRobert Barrowcliff
    • H01L27/15
    • H05B33/145
    • An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.
    • 提供了一种电致发光(EL)器件和用于制造具有纳米尖端电极的所述器件的方法。 该方法包括:形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。 纳米尖端可以具有约50纳米或更小的尖端基部尺寸,5至50nm范围内的尖端高度,以及每平方毫米大于100纳米尖端的纳米密度密度。 通常,纳米尖端由氧化铱(IrOx)纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。 在一个方面,Si磷光体层是SRSO层。 响应于SRSO退火步骤,形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。
    • 3. 发明申请
    • Non-volatile memory resistor cell with nanotip electrode
    • 带纳米尖电极的非易失性存储器电阻单元
    • US20060160304A1
    • 2006-07-20
    • US11039544
    • 2005-01-19
    • Sheng HsuFengyan ZhangGregory SteckerRobert Barrowcliff
    • Sheng HsuFengyan ZhangGregory SteckerRobert Barrowcliff
    • H01L21/336
    • H01L27/101H01L45/04H01L45/1233H01L45/1273H01L45/147H01L45/16H01L45/1675
    • A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.
    • 提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。 该方法包括:形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极,其中所述存储电阻材料置于所述第一和第二电极之间。 通常,纳米针是氧化铱(IrOx),并且具有约50纳米或更小的尖端基底尺寸,在5至50nm范围内的尖端高度,以及每平方微米大于100纳米尖端的纳米密度密度。 一方面,衬底材料可以是硅,氧化硅,氮化硅或贵金属。 使用金属有机化学气相沉积(MOCVD)工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。
    • 4. 发明申请
    • IRIDIUM OXIDE NANOSTRUCTURE PATTERNING
    • 氧化亚氮纳米结构图
    • US20060088993A1
    • 2006-04-27
    • US11013804
    • 2004-12-15
    • Fengyan ZhangGregory SteckerRobert BarrowcliffSheng Hsu
    • Fengyan ZhangGregory SteckerRobert BarrowcliffSheng Hsu
    • H01L21/4763H01L21/302
    • H01L21/31111B81C1/00111B82Y10/00
    • A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.
    • 提供了用于构图氧化铱(IrOx)纳米结构的方法。 该方法包括:在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常,第一区域由第一材料形成,第二区域由不同于第一材料的第二材料形成。 例如,第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。
    • 5. 发明申请
    • IRIDIUM OXIDE NANOSTRUCTURE
    • 氧化亚氮纳米结构
    • US20060124926A1
    • 2006-06-15
    • US11339876
    • 2006-01-26
    • Fengyan ZhangGregory SteckerRobert BarrowcliffSheng Hsu
    • Fengyan ZhangGregory SteckerRobert BarrowcliffSheng Hsu
    • H01L29/10H01L21/302
    • H01L21/31111B81C1/00111B82Y10/00
    • A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.
    • 提供了用于构图氧化铱(IrOx)纳米结构的方法。 该方法包括:形成邻近第二区域的衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常,第一区域由第一材料形成,第二区域由不同于第一材料的第二材料形成。 例如,第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。
    • 7. 发明申请
    • Photovoltaic structure with a conductive nanowire array electrode
    • 具有导电纳米线阵列电极的光伏结构
    • US20070111368A1
    • 2007-05-17
    • US11280423
    • 2005-11-16
    • Fengyan ZhangRobert BarrowcliffSheng Hsu
    • Fengyan ZhangRobert BarrowcliffSheng Hsu
    • H01L51/40H01L21/00
    • H01L51/4213B82Y10/00H01L51/0046H01L51/0048H01L51/4226H01L51/4233H01L51/441Y02E10/52Y02E10/549
    • A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).
    • 提供光伏(PV)结构以及用于形成具有导电纳米线阵列电极的PV结构的方法。 该方法包括:形成具有导电纳米线的底电极; 形成覆盖在纳米线上的第一掺杂剂型(即n型)的第一半导体层; 形成与所述第一掺杂剂类型(即,p型)相反的第二掺杂剂类型的第二半导体层,所述第二掺杂剂类型覆盖所述第一半导体层; 以及形成覆盖所述第二半导体层的顶部电极。 第一和第二半导体层可以是诸如导电聚合物,具有富勒烯衍生物的共轭聚合物和诸如CdSe,CdS,二氧化钛或ZnO的无机材料的材料。 导电纳米线可以是诸如IrO 2,In 2 O 3,SnO 2,或铟的材料 氧化锡(ITO)。
    • 8. 发明申请
    • Ambient environment nanowire sensor
    • 环境纳米线传感器
    • US20080010707A1
    • 2008-01-10
    • US11264113
    • 2005-11-01
    • Fengyan ZhangRobert BarrowcliffJong-Jan LeeSheng Hsu
    • Fengyan ZhangRobert BarrowcliffJong-Jan LeeSheng Hsu
    • C30B25/00C30B23/00C30B28/12
    • B81C1/00182B81B2201/0214Y10S977/712Y10S977/762
    • An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.
    • 提供了一种周围环境纳米线传感器和相应的制造方法。 该方法包括:形成诸如硅(Si)或玻璃的衬底; 生长纳米线 沉积覆盖在纳米线上的绝缘体层; 蚀刻以暴露纳米线的尖端; 形成图案化的金属电极,其边缘覆盖在纳米线的尖端上; 并且蚀刻以暴露电极边缘下方的纳米线。 纳米线可以是诸如IrO 2,TiO 2,InO,ZnO,SnO 2,Sb 2,N 2的材料 例如,在实施例3中,可以举出例如“O 3”,“3”,“ 绝缘体层可以是旋涂玻璃(SOG)或低k电介质。 一方面,所得结构包括从掺杂衬底区域生长的暴露的纳米线和具有嵌入的纳米线的绝缘体芯。 在不同的方面,该方法形成覆盖衬底的生长促进层。 所得结构包括从选择性形成的生长促进层生长的暴露的纳米线。