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1. 发明授权

US06670265B2 Low K dielectic etch in high density plasma etcher 失效
标题翻译：在高密度等离子体蚀刻机中的低K电介质蚀刻
公开(公告)号：US06670265B2
公开(公告)日：2003-12-30
申请号：US09326744
申请日：1999-06-04
申请人： Fei Wang , James K. Kai , Angela T. Hui
发明人： Fei Wang , James K. Kai , Angela T. Hui
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76804
摘要： An integrated circuit wafer and a manufacturing process for etching low K spin-on dielectrics such as HSQ in a High Density Plasma etch reactor utilizes roof and wall temperature to improve across-the-wafer uniformity, and a mixture of C4F8 and C2F6 etch gases to eliminate mid via etch stop and to maintain selectivity over underlying etch-stop layers.
摘要翻译：用于在高密度等离子体蚀刻反应器中蚀刻低K自旋电介质如HSQ的集成电路晶片和制造工艺利用屋顶和壁温度来改善晶片间的均匀性，并且将C4F8和C2F6的气体混合物蚀刻到通过蚀刻停止消除中间，并保持对底层蚀刻停止层的选择性。

2. 发明授权

US06400030B1 Self-aligning vias for semiconductors 有权
标题翻译：半导体自对准通孔
公开(公告)号：US06400030B1
公开(公告)日：2002-06-04
申请号：US09583817
申请日：2000-05-30
申请人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
发明人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76802
摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.
摘要翻译：具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。阻挡氮化物层以矩形通孔结构进行氮化蚀刻，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

3. 发明授权

US06475847B1 Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：使用衬垫氧化物层形成具有自对准触点的半导体器件的方法
公开(公告)号：US06475847B1
公开(公告)日：2002-11-05
申请号：US10109526
申请日：2002-03-27
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种缩小半导体器件并最小化自动掺杂问题的方法。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触，并且用作电介质层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

4. 发明授权

US06420752B1 Semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：具有使用衬垫氧化物层的自对准触点的半导体器件
公开(公告)号：US06420752B1
公开(公告)日：2002-07-16
申请号：US09502163
申请日：2000-02-11
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种用于最小化自动掺杂问题的半导体器件。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

5. 发明申请

US20120139023A1 METHOD AND APPARATUS FOR NAND MEMORY WITH RECESSED SOURCE/DRAIN REGION 审中-公开
标题翻译：用于存储源/漏区的NAND存储器的方法和装置
公开(公告)号：US20120139023A1
公开(公告)日：2012-06-07
申请号：US12960411
申请日：2010-12-03
申请人： Chun CHEN , Angela T. Hui , Fei Wang
发明人： Chun CHEN , Angela T. Hui , Fei Wang
IPC分类号： H01L29/78 , H01L21/04 , G06F17/50
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/1157 , H01L29/792
摘要： A method and apparatus for a flash memory is provided. A NAND flash memory array includes a cell body, a first selective gate, and a first edge line. The cell body includes recessed doped source/drain region between the first selective gate and the first edge word line.
摘要翻译：提供了一种用于闪速存储器的方法和装置。 NAND闪存阵列包括单元体，第一选择栅极和第一边缘线。电池体包括在第一选择栅极和第一边缘字线之间的凹入的掺杂源极/漏极区域。

6. 发明授权

US6124201A Method for manufacturing semiconductors with self-aligning vias 失效
标题翻译：具有自对准通孔的半导体制造方法
公开(公告)号：US6124201A
公开(公告)日：2000-09-26
申请号：US097126
申请日：1998-06-12
申请人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
发明人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
IPC分类号： H01L21/60 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76802
摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. He stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.
摘要翻译：具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。他停止氮化物层是以矩形通孔结构蚀刻氮化物，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

7. 发明授权

US06632707B1 Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning 有权
标题翻译：使用CVD有机BARC形成互连结构以减轻中毒的方法
公开(公告)号：US06632707B1
公开(公告)日：2003-10-14
申请号：US10058227
申请日：2002-01-29
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.
摘要翻译：在沟槽掩模形成期间消除通孔中毒的在半导体器件中形成金属互连结构的方法使用隔离低k绝缘膜的CVD有机BARC。 CVD有机BARC沉积在低k电介质膜和通孔中。一旦在CVD有机BARC上形成了沟槽掩模，就可以以与沟槽掩模层的光致抗蚀剂相同的工艺去除CVD有机BARC。由于CVD有机BARC的存在基本上消除了通孔中毒和抵抗浮渣，所以将形成一个正确形成的沟槽。

8. 发明授权

US06424039B1 Dual damascene process using sacrificial spin-on materials 有权
公开(公告)号：US06424039B1
公开(公告)日：2002-07-23
申请号：US09532731
申请日：2000-03-22
申请人： Fei Wang , Bhanwar Singh , James K. Kai
发明人： Fei Wang , Bhanwar Singh , James K. Kai
IPC分类号： H01L2348
摘要： A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

9. 发明授权

US06297167B1 In-situ etch of multiple layers during formation of local interconnects 失效
标题翻译：在局部互连形成期间原位蚀刻多层
公开(公告)号：US06297167B1
公开(公告)日：2001-10-02
申请号：US08924574
申请日：1997-09-05
申请人： Fei Wang , James K. Kai , William G. En
发明人： Fei Wang , James K. Kai , William G. En
IPC分类号： H01L21027
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76895
摘要： An in-situ etching process for creating local interconnects in a semiconductor device includes using a single etching tool to: etch through a masked dielectric layer to a stop layer using a mixture of C4F8/CH3F/Ar gasses; etch away the mask layer using a mixture of O2/Ar gasses; and etch through the stop layer using a mixture of CH3F/O2 gasses. The semiconductor device is not removed from the etching tool between the different etchings. The method then includes depositing conductive material to form local interconnects within the openings that were etched.
摘要翻译：用于在半导体器件中产生局部互连的原位蚀刻工艺包括使用单个蚀刻工具：使用C4F8 / CH3F / Ar气体的混合物将掩模的介电层蚀刻到停止层; 使用O 2 / Ar气体的混合物蚀刻掩模层; 并使用CH3F / O2气体的混合物蚀刻通过停止层。在不同蚀刻之间，半导体器件不会从蚀刻工具中移除。该方法然后包括沉积导电材料以在被蚀刻的开口内形成局部互连。

10. 发明授权

US6057239A Dual damascene process using sacrificial spin-on materials 失效
公开(公告)号：US6057239A
公开(公告)日：2000-05-02
申请号：US992537
申请日：1997-12-17
申请人： Fei Wang , Bhanwar Singh , James K. Kai
发明人： Fei Wang , Bhanwar Singh , James K. Kai
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76808
摘要： A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

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