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1. 发明授权

US5920796A In-situ etch of BARC layer during formation of local interconnects 失效
标题翻译：局部互连形成期间BARC层的原位蚀刻
公开(公告)号：US5920796A
公开(公告)日：1999-07-06
申请号：US924572
申请日：1997-09-05
申请人： Fei Wang , Allison Holbrook , James K. Kai
发明人： Fei Wang , Allison Holbrook , James K. Kai
IPC分类号： H01L21/027 , H01L21/311 , H01L21/768 , H01L21/306
CPC分类号： H01L21/31116 , H01L21/0276 , H01L21/76895
摘要： An in-situ etching process for creating local interconnects in a semiconductor device includes using one etching tool to: etch through an organic, or inorganic BARC layer using O.sub.2 gas, or C.sub.2 F.sub.6 /O.sub.2 gases, respectively; a masked dielectric layer to a stop layer using a mixture of C.sub.4 F.sub.8, CH.sub.3 F and argon (Ar) gasses; etch away the mask layer using a mixture of O.sub.2 and Ar gasses; and, etch through the stop layer using a mixture of CH.sub.3 F gas and O.sub.2 gas. Remaining portions of the BARC layer, whether organic or inorganic, are also removed during the in-situ etching process using appropriate gases. The method then includes depositing conductive material within the openings that were etched to form local interconnects.
摘要翻译：用于在半导体器件中产生局部互连的原位蚀刻工艺包括使用一个蚀刻工具来分别使用O 2气体或C 2 F 6 / O 2气体蚀刻通过有机或无机BARC层; 使用C 4 F 8，CH 3 F和氩（Ar）气体的混合物将阻挡层的掩模介电层; 使用O 2和Ar气体的混合物蚀刻掩模层; 并且使用CH 3 F气体和O 2气体的混合物蚀刻通过停止层。无论是有机还是无机，BARC层的剩余部分在原位蚀刻工艺中也被使用合适的气体除去。然后，该方法包括在蚀刻形成局部互连的开口内沉积导电材料。

2. 发明授权

US06358362B1 Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process 有权
标题翻译：用于确定原位局部互连蚀刻工艺的端点的方法和装置
公开(公告)号：US06358362B1
公开(公告)日：2002-03-19
申请号：US09515321
申请日：2000-02-29
申请人： William G. En , Allison Holbrook , Fei Wang
发明人： William G. En , Allison Holbrook , Fei Wang
IPC分类号： G01I346
CPC分类号： B24B37/013 , H01J37/32935 , H01J37/32963 , H01L21/67253 , H01L22/26
摘要： An arrangement is provided for collecting, measuring and analyzing at least two specific wavelengths of optical emissions produced while etching a semiconductor wafer in a plasma chamber to determine an optimal endpoint for the etching process. The arrangement includes a sensor for gathering optical emissions, an interface for converting the intensity of optical emissions into corresponding electrical signals, and a controller for determining an optimal endpoint based on the corresponding electrical signals for the two specific wavelengths and other predetermined threshold data.
摘要翻译：提供了一种用于收集，测量和分析在蚀刻等离子体室中的半导体晶片时产生的至少两个特定波长的光发射以确定用于蚀刻工艺的最佳端点的装置。该装置包括用于收集光发射的传感器，用于将光发射强度转换成相应电信号的接口，以及用于基于两个特定波长和其它预定阈值数据的对应电信号确定最佳端点的控制器。

3. 发明授权

US6060328A Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process 失效
公开(公告)号：US6060328A
公开(公告)日：2000-05-09
申请号：US924569
申请日：1997-09-05
申请人： William G. En , Allison Holbrook , Fei Wang
发明人： William G. En , Allison Holbrook , Fei Wang
IPC分类号： H01J37/32 , H01L21/00 , H01L21/66 , G01B11/02 , G01R31/26
CPC分类号： B24B37/013 , H01J37/32935 , H01J37/32963 , H01L21/67253 , H01L22/26
摘要： An arrangement is provided for collecting, measuring and analyzing at least two specific wavelengths of optical emissions produced while etching a semiconductor wafer in a plasma chamber to determine an optimal endpoint for the etching process. The arrangement includes a sensor for gathering optical emissions, an interface for converting the intensity of optical emissions into corresponding electrical signals, and a controller for determining an optimal endpoint based on the corresponding electrical signals for the two specific wavelengths and other predetermined threshold data.

4. 发明授权

US06670265B2 Low K dielectic etch in high density plasma etcher 失效
标题翻译：在高密度等离子体蚀刻机中的低K电介质蚀刻
公开(公告)号：US06670265B2
公开(公告)日：2003-12-30
申请号：US09326744
申请日：1999-06-04
申请人： Fei Wang , James K. Kai , Angela T. Hui
发明人： Fei Wang , James K. Kai , Angela T. Hui
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76804
摘要： An integrated circuit wafer and a manufacturing process for etching low K spin-on dielectrics such as HSQ in a High Density Plasma etch reactor utilizes roof and wall temperature to improve across-the-wafer uniformity, and a mixture of C4F8 and C2F6 etch gases to eliminate mid via etch stop and to maintain selectivity over underlying etch-stop layers.
摘要翻译：用于在高密度等离子体蚀刻反应器中蚀刻低K自旋电介质如HSQ的集成电路晶片和制造工艺利用屋顶和壁温度来改善晶片间的均匀性，并且将C4F8和C2F6的气体混合物蚀刻到通过蚀刻停止消除中间，并保持对底层蚀刻停止层的选择性。

5. 发明授权

US06632707B1 Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning 有权
标题翻译：使用CVD有机BARC形成互连结构以减轻中毒的方法
公开(公告)号：US06632707B1
公开(公告)日：2003-10-14
申请号：US10058227
申请日：2002-01-29
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.
摘要翻译：在沟槽掩模形成期间消除通孔中毒的在半导体器件中形成金属互连结构的方法使用隔离低k绝缘膜的CVD有机BARC。 CVD有机BARC沉积在低k电介质膜和通孔中。一旦在CVD有机BARC上形成了沟槽掩模，就可以以与沟槽掩模层的光致抗蚀剂相同的工艺去除CVD有机BARC。由于CVD有机BARC的存在基本上消除了通孔中毒和抵抗浮渣，所以将形成一个正确形成的沟槽。

6. 发明授权

US06424039B1 Dual damascene process using sacrificial spin-on materials 有权
公开(公告)号：US06424039B1
公开(公告)日：2002-07-23
申请号：US09532731
申请日：2000-03-22
申请人： Fei Wang , Bhanwar Singh , James K. Kai
发明人： Fei Wang , Bhanwar Singh , James K. Kai
IPC分类号： H01L2348
摘要： A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

7. 发明授权

US06297167B1 In-situ etch of multiple layers during formation of local interconnects 失效
标题翻译：在局部互连形成期间原位蚀刻多层
公开(公告)号：US06297167B1
公开(公告)日：2001-10-02
申请号：US08924574
申请日：1997-09-05
申请人： Fei Wang , James K. Kai , William G. En
发明人： Fei Wang , James K. Kai , William G. En
IPC分类号： H01L21027
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76895
摘要： An in-situ etching process for creating local interconnects in a semiconductor device includes using a single etching tool to: etch through a masked dielectric layer to a stop layer using a mixture of C4F8/CH3F/Ar gasses; etch away the mask layer using a mixture of O2/Ar gasses; and etch through the stop layer using a mixture of CH3F/O2 gasses. The semiconductor device is not removed from the etching tool between the different etchings. The method then includes depositing conductive material to form local interconnects within the openings that were etched.
摘要翻译：用于在半导体器件中产生局部互连的原位蚀刻工艺包括使用单个蚀刻工具：使用C4F8 / CH3F / Ar气体的混合物将掩模的介电层蚀刻到停止层; 使用O 2 / Ar气体的混合物蚀刻掩模层; 并使用CH3F / O2气体的混合物蚀刻通过停止层。在不同蚀刻之间，半导体器件不会从蚀刻工具中移除。该方法然后包括沉积导电材料以在被蚀刻的开口内形成局部互连。

8. 发明授权

US6057239A Dual damascene process using sacrificial spin-on materials 失效
公开(公告)号：US6057239A
公开(公告)日：2000-05-02
申请号：US992537
申请日：1997-12-17
申请人： Fei Wang , Bhanwar Singh , James K. Kai
发明人： Fei Wang , Bhanwar Singh , James K. Kai
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76808
摘要： A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

9. 发明授权

US06514860B1 Integration of organic fill for dual damascene process 有权
标题翻译：有机填料的整合用于双镶嵌工艺
公开(公告)号：US06514860B1
公开(公告)日：2003-02-04
申请号：US09892750
申请日：2001-06-28
申请人： Lynne A. Okada , Fei Wang , James K. Kai
发明人： Lynne A. Okada , Fei Wang , James K. Kai
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, depositing an organic fill material in the opening and removing a portion of the organic fill material before etching the second dielectric layer to form a trench. The organic fill material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature.
摘要翻译：制造半导体器件的方法包括：在第一层上形成第二阻挡层，在第二阻挡层上形成第一介电层，在第一介电层上形成第二电介质层，蚀刻第一和第二电介质层，形成第通过第一电介质层和第二电介质层开口，在蚀刻第二介电层之前将有机填充材料沉积在开口中并去除一部分有机填充材料以形成沟槽。然后可以完全去除有机填充材料，并且蚀刻第二阻挡层以暴露第一层。然后用导电材料填充沟槽和通孔以形成特征。

10. 外观设计

USD985928S1 Sandbag 有权
公开(公告)号：USD985928S1
公开(公告)日：2023-05-16
申请号：US29881670
申请日：2023-01-05
申请人： Fei Wang
设计人： Fei Wang
摘要： FIG. 1 is a first perspective view of a sandbag showing my new design;
FIG. 2 is a second perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a back view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top view thereof;
FIG. 8 is a bottom view thereof;
FIG. 9 is an enlarged view of the selected portion 9 in FIG. 1;
FIG. 10 is an enlarged view of the selected portion 10 in FIG. 2; and,
FIG. 11 is an enlarged view of the selected portion 11 in FIG. 4.
The broken lines shown in the drawings depict portions of the sandbag that form no part of the claimed design.
The dash-dot-dash broken lines depict cut lines of the enlarged portions and form no part of the claimed design.

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