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1. 发明授权

US06654301B2 Multiple discharge capable bit line 有权
标题翻译：多放电能力位线
公开(公告)号：US06654301B2
公开(公告)日：2003-11-25
申请号：US09965307
申请日：2001-09-27
申请人： Farzad Chehrazi , Shaishav A. Desai , Anup S. Mehta , Devendra N. Tawari
发明人： Farzad Chehrazi , Shaishav A. Desai , Anup S. Mehta , Devendra N. Tawari
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/12
摘要： A bit line that has a feedback path from the bit line to a storage cell on the bit line is provided. The feedback path allows the bit line to discharge through a discharge device that is connected to a non-discharging local bit line. Further, a discharge device capable of discharging a global bit line even when a storage cell connected to the discharge device is not being evaluated is provided. Further, a method to perform a memory array operation by discharging a bit line using multiple discharge devices is provided.
摘要翻译：提供了具有从位线到位线上的存储单元的反馈路径的位线。反馈路径允许位线通过连接到非放电局部位线的放电装置放电。此外，即使在没有评估连接到放电装置的存储单元的情况下，也能够提供能够对全局位线进行放电的放电装置。此外，提供了通过使用多个放电装置放电位线来执行存储器阵列操作的方法。

2. 发明授权

US06282556B1 High performance pipelined data path for a media processor 有权
标题翻译：用于媒体处理器的高性能流水线数据路径
公开(公告)号：US06282556B1
公开(公告)日：2001-08-28
申请号：US09451669
申请日：1999-11-30
申请人： Farzad Chehrazi , Vojin G. Oklobdzija
发明人： Farzad Chehrazi , Vojin G. Oklobdzija
IPC分类号： G06F752
CPC分类号： G06F7/5324 , G06F7/4991 , G06F7/49921 , G06F7/49994 , G06F7/5338 , G06F7/544 , G06F7/57 , G06F9/30014 , G06F9/30021 , G06F9/30025 , G06F9/30145 , G06F2207/382 , G06F2207/3828 , G06F2207/3884 , G06F2207/5442
摘要： A pipelined data path architecture for use, in one embodiment, in a multimedia processor. The data path architecture requires a maximum of two execution pipestages to perform all instructions including wide data format multiply instructions and specially adapted multimedia instructions, such as the sum of absolute differences (SABD) instruction and other multiply with add (MADD) instructions. The data path architecture includes two wide data format input registers that feed four partitioned 32×32 multiplier circuits. Within two pipestages, the multiply circuit can perform one 128×128 multiply operation, four 32×32 multiply operations, eight 16×16 multiply operations or sixteen 8×8 multiply operations in parallel. The multiply circuit contains a compressor tree which generates a 256-bit sum and a 256-bit carry vector. These vectors are supplied to four 64-bit carry propagate adder circuits which generate the multiply results. When the data path architecture is performing specially adapted multimedia instructions the input registers are supplied to a pipelined logic unit containing adders, subtractors, shifters, average/round/absolute value circuits, and other logic operation circuits, compressor circuits and multiplexers. The output of the pipelined logic unit is then fed to the four 64-bit carry propagate adder circuits. In this way, the adder circuits of the multiply operation can be effectively used to also process the specially adapted multimedia instructions thereby saving IC area. Multiply circuitry is disabled to save power when the data path architecture is not processing a multiplication instruction.
摘要翻译：在一个实施例中，在多媒体处理器中使用的流水线数据路径架构。数据路径架构最多需要两个执行管道来执行所有指令，包括宽数据格式乘法指令和特别适应的多媒体指令，例如绝对差（SABD）指令和其他乘以加法（MADD）指令的和。数据路径架构包括两个宽的数据格式输入寄存器，它们提供四个分区的32x32乘法器电路。在两个管道中，乘法电路可以并行执行一个128x128乘法运算，四个32x32乘法运算，八个16x16乘法运算或十八个8x8乘法运算。乘法电路包含一个产生256位和的256位进位向量的压缩器树。这些矢量被提供给产生乘法结果的四个64位进位传播加法器电路。当数据路径架构执行特别适应的多媒体指令时，输入寄存器被提供给包含加法器，减法器，移位器，平均/舍入/绝对值电路和其它逻辑运算电路，压缩器电路和多路复用器的流水线逻辑单元。然后将流水线逻辑单元的输出馈送到四个64位进位传播加法器电路。以这种方式，乘法运算的加法器电路可以有效地用于处理特别适应的多媒体指令，从而节省IC区域。当数据路径架构不处理乘法指令时，禁用乘法电路以节省电力。

3. 发明授权

US06243728B1 Partitioned shift right logic circuit having rounding support 有权
标题翻译：具有四舍五入支持的分区右移逻辑电路
公开(公告)号：US06243728B1
公开(公告)日：2001-06-05
申请号：US09351273
申请日：1999-07-12
申请人： Aamir Alam Farooqui , Vojin G. Oklobdzija , Farzad Chehrazi , Wei-Jen Li , Andy W. Yu
发明人： Aamir Alam Farooqui , Vojin G. Oklobdzija , Farzad Chehrazi , Wei-Jen Li , Andy W. Yu
IPC分类号： G06F501
CPC分类号： G06F7/505 , G06F5/015 , G06F7/49947 , G06F7/49952
摘要： A partitioned shift right logic circuit that is programmable and contains rounding support. The circuit of the present invention accepts a 32-bit value and a shift amount and then performs a right shift operation on the 32-bits and automatically rounds the result(s). Signed or unsigned values can be accepted. The right shift circuit is partitioned so that the 32-bit value can represent: (1) a single 32-bit number; or (2) two 16-bit values. A 1 bit selection input indicates the particular partition format. In operation, if the input value is not negative, then one (“1”) is added at the guard bit position and a right shift with truncate is performed. If the input is negative and the guard bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is one, then one is added at the guard bit position and a right shift with truncate is performed. The shift circuitry used by the present invention is fully partitioned to accept word or half-word input and contains multiple cascaded multiplexer stages for performing partitioned right shifting and supports signed shifting. Each multiplexer stage can be programmed to perform a selected shift amount (including 0 shift). The right shift circuit of the present invention can be used in multi-media applications and can also be used for general purpose and VLIW (very long instruction word) processor without performance degradation.
摘要翻译：分配的右移逻辑电路，可编程并包含四舍五入支持。本发明的电路接受32位值和移位量，然后对32位执行右移操作，并自动舍入结果。可以接受签名或无符号值。右移位电路被分区，使得32位值可以表示为：（1）单个32位数; 或（2）两个16位值。 1位选择输入表示特定的分区格式。在操作中，如果输入值不为负，则在保护位位置添加一个（“1”），并执行具有截断的右移位。如果输入为负并且保护位为零，则不进行任何加法，并且执行具有截断的右移位。如果输入为负，保护位为1，粘滞位为零，则不进行加法，并执行带截断的右移位。如果输入为负并且保护位为1，粘滞位为1，则在保护位位置添加一个，并执行带有截断的右移位。本发明使用的移位电路被完全划分为接受字或半字输入，并且包含用于执行分区右移的多个级联多路复用器级并且支持符号移位。每个复用器级可以被编程以执行所选择的移位量（包括0移位）。本发明的右移位电路可用于多媒体应用，也可用于通用和VLIW（非常长的指令字）处理器，而不会降低性能。

4. 发明授权

US06353843B1 High performance universal multiplier circuit 有权
标题翻译：高性能通用乘法器电路
公开(公告)号：US06353843B1
公开(公告)日：2002-03-05
申请号：US09415485
申请日：1999-10-08
申请人： Farzad Chehrazi , Vojin G. Oklobdzija , Aamir A. Farooqui
发明人： Farzad Chehrazi , Vojin G. Oklobdzija , Aamir A. Farooqui
IPC分类号： G06F752
CPC分类号： G06F7/5324 , G06F7/49994 , G06F7/5338 , G06F2207/382
摘要： A partitioned multiplier circuit which is designed for high speed operations. The multiplier of the present invention can perform one 32×32 bit multiplication, two 16×16 bit multiplications (simultaneously) or four 8×8 bit multiplications (simultaneously) depending on input partitioning signals. The time required to perform either the 32×32 bit or the 16×16 bit or the 8×8 bit multiplications is constant. Therefore, multiplication results are available with a constant latency regardless of operand bit-size. In one embodiment, the latency is two clock cycles but the multiplier circuit has a throughput of one clock cycle due to pipelining. The input operands can be signed or unsigned. The hardware is partitioned without any significant increase in the delay or area and the multiplier can provide six different modes of operation. In one embodiment, Booth encoding is used for the generation of 17 partial products which are compressed using a compression tree into two 64-bit values. This is performed in the first pipeline stage to generate a sum and a carry vector. These values are then added, in the second pipestage, using a carry propagate adder circuit to provide a single 64-bit result. In the case of 16×16 bit multiplication, the 64-bit result contains two 32-bit results. In the case of 8×8 bit multiplication, the 64-bit result contains four 16-bit results. Due to its high operating speed, the multiplier circuit is advantageous for use in multi-media applications, such as audio/visual rendering and playback.
摘要翻译：分频乘法电路，专为高速运行而设计。根据输入的分频信号，本发明的乘法器可以执行一个32×32位乘法，两次16×16位乘法（同时）或四个8×8位乘法（同时）。执行32x32位或16x16位或8x8位乘法所需的时间是常数。因此，无论操作数位大小如何，乘法结果都可以使用恒定的延迟。在一个实施例中，等待时间是两个时钟周期，但乘法器电路由于流水线而具有一个时钟周期的吞吐量。输入操作数可以是有符号的或无符号的。硬件被分配，而延迟或区域没有任何显着增加，乘法器可以提供六种不同的操作模式。在一个实施例中，布斯编码用于生成使用压缩树压缩为两个64位值的17个部分乘积。这在第一流水线阶段执行以产生和和进位向量。然后，在第二个管道中，使用进位传播加法器电路来添加这些值，以提供单个64位结果。在16×16位乘法的情况下，64位结果包含两个32位结果。在8×8位乘法的情况下，64位结果包含四个16位结果。由于其高的操作速度，乘法器电路有利于在多媒体应用中使用，例如音频/视觉呈现和回放。

5. 发明授权

US06301599B1 Multiplier circuit having an optimized booth encoder/selector 有权
标题翻译：具有优化的展位编码器/选择器的乘法器电路
公开(公告)号：US06301599B1
公开(公告)日：2001-10-09
申请号：US09280176
申请日：1999-03-29
申请人： Farzad Chehrazi , Vojin G. Oklobdzija , Aamir Alam Farooqui
发明人： Farzad Chehrazi , Vojin G. Oklobdzija , Aamir Alam Farooqui
IPC分类号： G06F752
CPC分类号： G06F7/5338
摘要： An improved Booth encoder/selector circuit having an optimized critical path. The Booth encoder has a number of inverters coupled to several of the input multiplier bits. The inverted/non-inverted multiplier bits are then fed as inputs to NAND gates as well as a series of pass gates. The outputs of the pass gates are then fed as inputs to other NAND gates. The output from the NAND gates serve as control signals for controlling the Booth selector. The Booth selector is comprised of inverters and pass gates. Multiplicand bits are input to the pass gates. The control signals generated by the Booth encoder are selectively coupled to the inverters and pass gates such that they control which one of a plurality of multiplicand bits are selected for output. Basically, the Booth selector functions as a multiplexer whereby one of the following is output: the multiplicand bit is multiplied by zero, multiplied by one, multiplied by negative one, multiplied by two, or multiplied by negative two. The Booth encoder/selector is used in a multiplier circuit to minimize the number of partial products. An adder is then used to sum all of the partial products to arrive at the final answer. In the present invention, the critical path has been optimized such that the overall speed of the multiplier is greatly improved.
摘要翻译：具有优化的关键路径的改进的布斯编码器/选择器电路。布斯编码器具有耦合到多个输入乘法器位的多个反相器。然后将反相/非反相乘法器位作为输入馈送到NAND门以及一系列通路。然后将通过栅极的输出作为输入馈送到其他NAND门。来自NAND门的输出用作控制Booth选择器的控制信号。展位选择器由逆变器和通过门组成。乘数位被输入到通过门。由布斯编码器产生的控制信号选择性地耦合到反相器并传递门，使得它们控制多个被乘数位中的哪一个被选择用于输出。基本上，展位选择器用作多路复用器，其中输出以下之一：被乘数位乘以零乘以1，乘以负1乘以2乘以乘以2。 Booth编码器/选择器用于乘法器电路中以最小化部分乘积的数量。然后使用加法器来求出所有部分乘积以得出最终答案。在本发明中，关键路径已被优化，使得乘法器的总体速度大大提高。

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