专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06931122B2 Single transformer hybrid system and method 有权
标题翻译：单变压器混合系统及方法
公开(公告)号：US06931122B2
公开(公告)日：2005-08-16
申请号：US10649224
申请日：2003-08-26
申请人： Faramarz Sabouri , Ali Ghahary
发明人： Faramarz Sabouri , Ali Ghahary
IPC分类号： H03H7/48 , H03H11/36 , H04B1/58 , H04L25/02 , H04L25/08 , H04L27/00 , H04M9/08
CPC分类号： H04L27/0002 , H03H7/48 , H03H11/36 , H04B1/581 , H04B1/583 , H04L25/0266 , H04L25/0272 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/085
摘要： A hybrid matching system is disclosed for use with a transmitter and receiver. The hybrid matching system includes a pair of transmitter output nodes, a pair of receiver input nodes, and a pair of terminals for interfacing to a transmission line. The system further includes a first impedance bridge portion including at least one inductor for coupling to the transmission line terminals via at least one transformer winding, and a second impedance bridge portion interposed between the pair of transmitter output nodes and the first impedance bridge portion, and interposed between the pair of receiver input nodes and the first impedance bridge portion.
摘要翻译：公开了与发射机和接收机一起使用的混合匹配系统。混合匹配系统包括一对发射机输出节点，一对接收机输入节点和用于与传输线接口的一对终端。该系统还包括第一阻抗桥接部分，其包括至少一个电感器，用于经由至少一个变压器绕组耦合到传输线端子，以及插入在该对发射器输出节点和第一阻抗桥接部分之间的第二阻抗桥接部分，以及插入在一对接收器输入节点和第一阻抗桥接部分之间。

2. 发明授权

US06731166B1 Power amplifier system with multiple primary windings 有权
标题翻译：具有多个初级绕组的功率放大器系统
公开(公告)号：US06731166B1
公开(公告)日：2004-05-04
申请号：US09994247
申请日：2001-11-26
申请人： Faramarz Sabouri , Reza Shariatdoust
发明人： Faramarz Sabouri , Reza Shariatdoust
IPC分类号： H03F368
CPC分类号： H03F3/211 , H03F3/45475 , H03F2200/541
摘要： The invention provides a power amplifier system including a plurality of amplifiers, a plurality of primary transformer windings, a single secondary transformer winding. Each of the plurality of amplifiers includes a differential input that is commonly coupled to a system input port, and each the plurality of amplifiers also includes a differential output. Each of the plurality of primary transformer windings is coupled to the differential output of one of the plurality of amplifiers. The single secondary transformer winding is inductively coupled to all of the primary transformer windings and provides a system output port to which a load may be coupled.
摘要翻译：本发明提供一种功率放大器系统，包括多个放大器，多个初级变压器绕组，单个次级变压器绕组。多个放大器中的每一个包括通常耦合到系统输入端口的差分输入，并且每个多个放大器还包括差分输出。多个初级变压器绕组中的每一个耦合到多个放大器之一的差分输出。单个次级变压器绕组电感耦合到所有初级变压器绕组，并提供负载耦合到的系统输出端口。

3. 发明授权

US08933858B2 Front end parallel resonant switch 有权
标题翻译：前端并联谐振开关
公开(公告)号：US08933858B2
公开(公告)日：2015-01-13
申请号：US13570895
申请日：2012-08-09
申请人： Faramarz Sabouri
发明人： Faramarz Sabouri
IPC分类号： H01Q1/50 , H01Q1/24 , H04B1/04 , H01Q9/14 , H04B1/00 , H03H7/38
CPC分类号： H01Q1/50 , H01Q1/242 , H01Q9/14 , H03H2007/386 , H04B1/0057 , H04B1/006 , H04B1/0458
摘要： A front end parallel resonant switch is disclosed. In an exemplary embodiment, an apparatus includes an inductor and a capacitor configured to couple a first RF transmission to an antenna, and at least one switch configured to connect the inductor to the capacitor to form a matching network when transmitting the first RF transmission from the antenna, and to connect the inductor to capacitor to form a parallel resonant circuit when transmitting a second RF transmission from the antenna.
摘要翻译：公开了一种前端并联谐振开关。在示例性实施例中，一种装置包括：电感器和配置成将第一RF传输耦合到天线的电容器;以及至少一个开关，其被配置为在将电感器发送到第一RF发射时从电容器连接到电容器以形成匹配网络天线，并且当从天线发送第二RF传输时，将电感器连接到电容器以形成并联谐振电路。

4. 发明申请

US20100093279A1 ELECTRONIC DEVICES FOR COMMUNICATION UTILIZING ENERGY DETECTION AND/OR FREQUENCY SYNTHESIS 审中-公开
标题翻译：用于通讯的电子设备，用于能源检测和/或频率合成
公开(公告)号：US20100093279A1
公开(公告)日：2010-04-15
申请号：US12251356
申请日：2008-10-14
申请人： Joel Benjamin Linsky , Gene Fong , Faramarz Sabouri , Eugene Yang , Desong Zhao , Mark Lane , Thomas P. Cargill
发明人： Joel Benjamin Linsky , Gene Fong , Faramarz Sabouri , Eugene Yang , Desong Zhao , Mark Lane , Thomas P. Cargill
IPC分类号： H04B7/00
CPC分类号： H04W52/029 , H03L7/183 , H03L7/193 , H03L7/23 , H03L2207/06 , H04W52/0245 , H04W68/00 , Y02D70/142 , Y02D70/144 , Y02D70/164
摘要： An electronic device for communication comprises a processor. The processor comprises a power scan module configured to receive an energy detection signal identifying detection of energy of a page signal or an inquiry signal. The power scan module is further configured to provide, upon receiving the energy detection signal, an instruction to perform a page scan or an inquiry scan.
摘要翻译：用于通信的电子设备包括处理器。处理器包括功率扫描模块，其被配置为接收识别寻呼信号或查询信号的能量的能量检测信号。功率扫描模块还被配置为在接收到能量检测信号时提供执行寻呼扫描或查询扫描的指令。

5. 发明授权

US06563445B1 Self-calibration methods and structures for pipelined analog-to-digital converters 有权
标题翻译：用于流水线模数转换器的自校准方法和结构
公开(公告)号：US06563445B1
公开(公告)日：2003-05-13
申请号：US09995967
申请日：2001-11-28
申请人： Faramarz Sabouri
发明人： Faramarz Sabouri
IPC分类号： H03M110
CPC分类号： H03M1/1061 , H03M1/0695 , H03M1/442
摘要： Self-calibration methods and structures are provided for pipelined ADCs which can be realized without requiring external measuring instruments or calibrators, without requiring major changes in pipeline structure and which can be rapidly obtained with stored calibration processes. In method embodiments, each of selected converter stages are calibrated by using succeeding stages as sub-ADCs which measure gain error at a transition step in a selected stage's residue transfer characteristic and saves the gain error as a calibration constant Ccal for that stage. After a first calibration constant Ccal has been obtained, the process is successively repeated for preceding converter stages except that previously-obtained calibration constants are multiplied by their respective stage's digital input signals Din to obtain weighted calibration constants Ccalwtd which are included in measured gain errors to thereby obtain preceding calibration constants Ccal.
摘要翻译：为流水线ADC提供了自校准方法和结构，无需外部测量仪器或校准器即可实现，无需管道结构的重大变化，并可通过存储的校准过程快速获得。在方法实施例中，通过使用后续级来对每个所选择的转换器级进行校准，作为在所选阶段的剩余传输特性中的转变步骤处测量增益误差的子ADC，并将增益误差保存为该级的校准常数Ccal。在获得第一校准常数Ccal之后，先前的转换器级继续重复该过程，除了先前获得的校准常数乘以它们各自的级数字输入信号Din以获得包括在测量的增益误差中的加权校准常数Ccalwtd 从而获得先前的校准常数Ccal。

6. 发明授权

US07015683B1 JFET switch select circuit 有权
标题翻译： JFET开关选择电路
公开(公告)号：US07015683B1
公开(公告)日：2006-03-21
申请号：US10969622
申请日：2004-10-20
申请人： Ojas M. Choksi , Bindu Gupta , Faramarz Sabouri
发明人： Ojas M. Choksi , Bindu Gupta , Faramarz Sabouri
IPC分类号： G05F3/16
CPC分类号： H03F3/45094 , H03F3/45475 , H03F3/72 , H03F2200/522 , H03F2200/78 , H03F2203/45028 , H03F2203/45136 , H03F2203/45318 , H03F2203/45374 , H03F2203/45454 , H03F2203/45526 , H03F2203/45616 , H03F2203/45618 , H03F2203/45641 , H03F2203/7206 , H03G1/0029 , H03K17/6871 , H03K17/6877 , H03K2217/0036
摘要： A JFET switch select circuit including a first current mirror system including a first high current mirror circuit referenced to high rail voltage and a first low current mirror circuit referenced to a low rail voltage, a second current mirror system including a second high current mirror circuit referenced to the high rail voltage and a second low current mirror circuit referenced to the low rail voltage, and a comparator circuit responsive to an input voltage and a reference voltage for directing current from a current supply circuit to one of the first and second high current mirror circuits and one of the first and second low current mirror circuits for saturating a switching device of one of the first and second high current mirror circuits to set a first output voltage proximate to a high rail voltage and for saturating a switching device of one of the first and second low current mirror circuits to set a second output voltage proximate a low rail voltage.
摘要翻译：一种JFET开关选择电路，包括第一电流镜系统，该第一电流镜系统包括以高轨电压为参考的第一高电流镜电路和以低轨电压为基准的第一低电流镜电路;第二电流镜系统，包括第二高电流镜电路，以及基于低轨电压的第二低电流镜电路，以及响应于输入电压和参考电压的比较器电路，用于将电流从电流供应电路引导到第一和第二高电流镜中的一个电路和第一和第二低电流镜像电路之一，用于饱和第一和第二高电流镜像电路中的一个的开关器件，以设置接近高电压电压的第一输出电压，并使第一和第二低电流镜像电路之一的开关器件饱和第一和第二低电流镜电路，以在低轨电压附近设置第二输出电压。

7. 发明申请

US20050113034A1 Line interface system 有权
标题翻译：线路接口系统
公开(公告)号：US20050113034A1
公开(公告)日：2005-05-26
申请号：US10787652
申请日：2004-02-26
申请人： Alfred Mangino , Ojas Choksi , Faramarz Sabouri
发明人： Alfred Mangino , Ojas Choksi , Faramarz Sabouri
IPC分类号： H04B1/58 , H04L25/02 , H04B1/46 , H01Q11/12 , H04B1/04
CPC分类号： H04B1/581 , H04L25/0272
摘要： A transceiver system is disclosed for use in a telecommunication system. The transceiver system includes a transmission circuit with a differential transmitter input coupled via a transmitter input stage to a differential input of a transmission amplifier in an embodiment. The transmitter input stage includes a trimmable resistor, one end of which is coupled to a positive transmit input signal, and the other end of which is coupled to a negative transmit input signal. The transceiver system also includes a receiver circuit with a differential receiver output coupled to a differential input of a receiver amplifier, and further includes a transmission line interface circuit coupled to a differential output of said transmission amplifier and to a differential input of said receiver amplifier. In accordance with other embodiments, the receiver amplifier includes an input stage that includes a first plurality of capacitors and a feedback circuit that includes a second plurality of capacitors.
摘要翻译：公开了一种在电信系统中使用的收发机系统。收发器系统包括在实施例中具有通过发射机输入级耦合到发射放大器的差分输入的差分发射机输入的发射电路。发射机输入级包括可调整电阻器，其一端耦合到正传输输入信号，另一端耦合到负发射输入信号。收发器系统还包括具有耦合到接收器放大器的差分输入的差分接收器输出的接收器电路，并且还包括耦合到所述发送放大器的差分输出和所述接收放大器的差分输入的传输线接口电路。根据其他实施例，接收机放大器包括包括第一多个电容器的输入级和包括第二多个电容器的反馈电路。

8. 发明授权

US06774723B2 Output stage with stable quiescent current 有权
标题翻译：输出级稳定静态电流
公开(公告)号：US06774723B2
公开(公告)日：2004-08-10
申请号：US10176023
申请日：2002-06-20
申请人： Faramarz Sabouri
发明人： Faramarz Sabouri
IPC分类号： H03F326
CPC分类号： H03F3/3066 , H03F1/307
摘要： A circuit for matching a first mirror transistor with a second mirror transistor in a current mirror includes a bias transistor and a diode connected transistor to match such mirror transistors. More particularly, the circuit is a part of an amplifier having an output with a quiescent voltage and at least one rail voltage. The first mirror transistor has a first terminal coupled to the output and a second terminal coupled to the at least one rail voltage. To effectuate its mirroring function, the bias transistor is coupled to a first terminal of the second mirror transistor, and the diode connected transistor is coupled to both a second terminal of the second mirror transistor and the at least one rail voltage. The bias transistor has a terminal with a quiescent voltage that is substantially equal to the quiescent voltage of the output.
摘要翻译：用于在电流镜中匹配第一反射镜晶体管和第二反射镜晶体管的电路包括偏置晶体管和二极管连接的晶体管以匹配这种反射镜晶体管。更具体地，电路是具有静态电压和至少一个轨电压的输出的放大器的一部分。第一反射镜晶体管具有耦合到输出的第一端子和耦合到至少一个导轨电压的第二端子。为了实现其镜像功能，偏置晶体管耦合到第二反射镜晶体管的第一端子，并且二极管连接的晶体管耦合到第二反射镜晶体管的第二端子和至少一个导轨电压。偏置晶体管具有基本上等于输出的静态电压的静态电压的端子。

9. 发明授权

US5909132A Resistance bridge and its use in conversion systems 失效
公开(公告)号：US5909132A
公开(公告)日：1999-06-01
申请号：US910429
申请日：1997-08-13
申请人： Frederick N. Trofimenkoff , Faramarz Sabouri , James W. Haslett
发明人： Frederick N. Trofimenkoff , Faramarz Sabouri , James W. Haslett
IPC分类号： G01B7/00 , G01R17/10 , H03H7/00 , H03K3/02 , H03K5/00 , H03M1/06 , G06F15/20
CPC分类号： G01R17/10
摘要： An electrical network creates a differential voltage signal and comprises a plurality of first impedance elements of substantially equal values which are connected to form an impedance bridge. The impedance of at least one of the first impedance elements changes in response to at least one selected external condition to which the first impedance elements are exposed. The network also comprises a second impedance element which has two nodes. The second impedance element is connected at these nodes between a first pair of the first impedance elements. The differential voltages are measured between these nodes and between another node or nodes with magnitudes and signs being dependent upon the change in the impedance of the first impedance elements.

10. 发明授权

US07072617B1 System and method for suppression of RFI interference 有权
标题翻译：用于抑制RFI干扰的系统和方法
公开(公告)号：US07072617B1
公开(公告)日：2006-07-04
申请号：US10850307
申请日：2004-05-19
申请人： Bindu Gupta , Faramarz Sabouri , Vladimir Friedman
发明人： Bindu Gupta , Faramarz Sabouri , Vladimir Friedman
IPC分类号： H04B1/10
CPC分类号： H04L25/085 , H03G3/3052 , H04L27/0002
摘要： A system and method for suppressing RFI receives a differential input signal Vd, and a signal Vcm which varies with the common mode component of Vd. Vcm is phase-shifted and then amplified with a programmable gain G1 to produce an output VA1. A subtractor produces an output Vsub which varies with Vd−VA1. Vsub is amplified with a programmable gain G2 to produce an output VA2. An analog input signal processing circuit receives VA2 at an input which has an associated maximum dynamic range. A processor adjusts G2 such that VA2 covers the maximum dynamic range, adjusts the phase shift and G1 to minimize VA2, and adjusts G2 to increase VA2 such that it again covers the maximum dynamic range. The RFI in Vd is substantially subtracted out, thereby enabling the full dynamic range of the analog input signal processing circuit to be employed in receiving Vd.
摘要翻译：用于抑制RFI的系统和方法接收差分输入信号V SUB，以及随着V D的共模分量而变化的信号V cc >。 VCI是相移的，然后用可编程增益G 1进行放大，以产生输出V A1。减法器产生随着V SUB-A1 A1变化的输出V SUB子。使用可编程增益G 2对V SUB子件进行放大，以产生输出V A2。模拟输入信号处理电路在具有相关最大动态范围的输入端接收V A2。处理器调整G 2使得V A2覆盖最大动态范围，调整相移和G 1使V A2最小化，并调整G 2以增加V _{A2 ，使其再次覆盖最大动态范围。基本上减去了V SUB中的RFI，从而使模拟输入信号处理电路的全动态范围能够用于接收V SUB。}

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式