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1. 发明申请

US20110279184A1 AREA EFFICIENT CONCURRENT MATCHING TRANSCEIVER 有权
标题翻译：区域有效的相互匹配收发器
公开(公告)号：US20110279184A1
公开(公告)日：2011-11-17
申请号：US12970210
申请日：2010-12-16
申请人： Ngar Loong A. Chan , Jonghoon Choi , Bindu Gupta
发明人： Ngar Loong A. Chan , Jonghoon Choi , Bindu Gupta
IPC分类号： H03F3/68 , H03F3/16
CPC分类号： H03F3/195 , H03F1/223 , H03F1/347 , H03F1/565 , H03F3/245 , H03F3/72 , H03F2200/294 , H03F2200/492 , H03F2200/537 , H03F2200/541 , H03F2203/7221 , H03H11/30 , H04B1/0458 , H04B1/18
摘要： An integrated circuit for transmit and receive matching is described. The integrated circuit includes a transmit amplifier. The transmit amplifier includes a first transistor, a second transistor and a first inductor. The first inductor couples the first transistor to the second transistor. The integrated circuit also includes a low noise amplifier. The low noise amplifier includes a third transistor, a fourth transistor, the first inductor, a second inductor, a third inductor and a transformer. The second inductor couples the first inductor to the third transistor. The third inductor couples the third transistor to ground.
摘要翻译：描述了用于发送和接收匹配的集成电路。集成电路包括发射放大器。发射放大器包括第一晶体管，第二晶体管和第一电感器。第一电感器将第一晶体管耦合到第二晶体管。该集成电路还包括一个低噪声放大器。低噪声放大器包括第三晶体管，第四晶体管，第一电感器，第二电感器，第三电感器和变压器。第二电感器将第一电感器耦合到第三晶体管。第三电感将第三晶体管耦合到地。

2. 发明授权

US07015683B1 JFET switch select circuit 有权
标题翻译： JFET开关选择电路
公开(公告)号：US07015683B1
公开(公告)日：2006-03-21
申请号：US10969622
申请日：2004-10-20
申请人： Ojas M. Choksi , Bindu Gupta , Faramarz Sabouri
发明人： Ojas M. Choksi , Bindu Gupta , Faramarz Sabouri
IPC分类号： G05F3/16
CPC分类号： H03F3/45094 , H03F3/45475 , H03F3/72 , H03F2200/522 , H03F2200/78 , H03F2203/45028 , H03F2203/45136 , H03F2203/45318 , H03F2203/45374 , H03F2203/45454 , H03F2203/45526 , H03F2203/45616 , H03F2203/45618 , H03F2203/45641 , H03F2203/7206 , H03G1/0029 , H03K17/6871 , H03K17/6877 , H03K2217/0036
摘要： A JFET switch select circuit including a first current mirror system including a first high current mirror circuit referenced to high rail voltage and a first low current mirror circuit referenced to a low rail voltage, a second current mirror system including a second high current mirror circuit referenced to the high rail voltage and a second low current mirror circuit referenced to the low rail voltage, and a comparator circuit responsive to an input voltage and a reference voltage for directing current from a current supply circuit to one of the first and second high current mirror circuits and one of the first and second low current mirror circuits for saturating a switching device of one of the first and second high current mirror circuits to set a first output voltage proximate to a high rail voltage and for saturating a switching device of one of the first and second low current mirror circuits to set a second output voltage proximate a low rail voltage.
摘要翻译：一种JFET开关选择电路，包括第一电流镜系统，该第一电流镜系统包括以高轨电压为参考的第一高电流镜电路和以低轨电压为基准的第一低电流镜电路;第二电流镜系统，包括第二高电流镜电路，以及基于低轨电压的第二低电流镜电路，以及响应于输入电压和参考电压的比较器电路，用于将电流从电流供应电路引导到第一和第二高电流镜中的一个电路和第一和第二低电流镜像电路之一，用于饱和第一和第二高电流镜像电路中的一个的开关器件，以设置接近高电压电压的第一输出电压，并使第一和第二低电流镜像电路之一的开关器件饱和第一和第二低电流镜电路，以在低轨电压附近设置第二输出电压。

3. 发明授权

US07072617B1 System and method for suppression of RFI interference 有权
标题翻译：用于抑制RFI干扰的系统和方法
公开(公告)号：US07072617B1
公开(公告)日：2006-07-04
申请号：US10850307
申请日：2004-05-19
申请人： Bindu Gupta , Faramarz Sabouri , Vladimir Friedman
发明人： Bindu Gupta , Faramarz Sabouri , Vladimir Friedman
IPC分类号： H04B1/10
CPC分类号： H04L25/085 , H03G3/3052 , H04L27/0002
摘要： A system and method for suppressing RFI receives a differential input signal Vd, and a signal Vcm which varies with the common mode component of Vd. Vcm is phase-shifted and then amplified with a programmable gain G1 to produce an output VA1. A subtractor produces an output Vsub which varies with Vd−VA1. Vsub is amplified with a programmable gain G2 to produce an output VA2. An analog input signal processing circuit receives VA2 at an input which has an associated maximum dynamic range. A processor adjusts G2 such that VA2 covers the maximum dynamic range, adjusts the phase shift and G1 to minimize VA2, and adjusts G2 to increase VA2 such that it again covers the maximum dynamic range. The RFI in Vd is substantially subtracted out, thereby enabling the full dynamic range of the analog input signal processing circuit to be employed in receiving Vd.
摘要翻译：用于抑制RFI的系统和方法接收差分输入信号V SUB，以及随着V D的共模分量而变化的信号V cc >。 VCI是相移的，然后用可编程增益G 1进行放大，以产生输出V A1。减法器产生随着V SUB-A1 A1变化的输出V SUB子。使用可编程增益G 2对V SUB子件进行放大，以产生输出V A2。模拟输入信号处理电路在具有相关最大动态范围的输入端接收V A2。处理器调整G 2使得V A2覆盖最大动态范围，调整相移和G 1使V A2最小化，并调整G 2以增加V _{A2 ，使其再次覆盖最大动态范围。基本上减去了V SUB中的RFI，从而使模拟输入信号处理电路的全动态范围能够用于接收V SUB。}

4. 发明授权

US08626084B2 Area efficient concurrent matching transceiver 有权
标题翻译：区域效率并发匹配收发器
公开(公告)号：US08626084B2
公开(公告)日：2014-01-07
申请号：US12970210
申请日：2010-12-16
申请人： Ngar Loong A Chan , Jonghoon Choi , Bindu Gupta
发明人： Ngar Loong A Chan , Jonghoon Choi , Bindu Gupta
IPC分类号： H04B1/44
CPC分类号： H03F3/195 , H03F1/223 , H03F1/347 , H03F1/565 , H03F3/245 , H03F3/72 , H03F2200/294 , H03F2200/492 , H03F2200/537 , H03F2200/541 , H03F2203/7221 , H03H11/30 , H04B1/0458 , H04B1/18
摘要： An integrated circuit for transmit and receive matching is described. The integrated circuit includes a transmit amplifier. The transmit amplifier includes a first transistor, a second transistor and a first inductor. The first inductor couples the first transistor to the second transistor. The integrated circuit also includes a low noise amplifier. The low noise amplifier includes a third transistor, a fourth transistor, the first inductor, a second inductor, a third inductor and a transformer. The second inductor couples the first inductor to the third transistor. The third inductor couples the third transistor to ground.
摘要翻译：描述了用于发送和接收匹配的集成电路。集成电路包括发射放大器。发射放大器包括第一晶体管，第二晶体管和第一电感器。第一电感器将第一晶体管耦合到第二晶体管。该集成电路还包括一个低噪声放大器。低噪声放大器包括第三晶体管，第四晶体管，第一电感器，第二电感器，第三电感器和变压器。第二电感器将第一电感器耦合到第三晶体管。第三电感将第三晶体管耦合到地。

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