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1. 发明申请

US20050167824A1 Integrated circuit with protective moat 有权
标题翻译：集成电路与防护护城河
公开(公告)号：US20050167824A1
公开(公告)日：2005-08-04
申请号：US10768796
申请日：2004-01-30
申请人： Fan Zhang , Kho Chok , Tae Lee , Xiaomei Bu , Meng Luo , Chian Sin , Yee Foong , Luona Goh , Liang Hsia , Huey Chong
发明人： Fan Zhang , Kho Chok , Tae Lee , Xiaomei Bu , Meng Luo , Chian Sin , Yee Foong , Luona Goh , Liang Hsia , Huey Chong
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L23/04 , H01L23/31 , H01L23/58 , H01L27/04
CPC分类号： H01L23/585 , H01L23/3192 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.
摘要翻译：制造集成电路的方法提供了具有半导体器件的衬底，并且包括在衬底和半导体器件上形成金属间电介质层。金属线形成在半导体器件的上方并与之接触，并且在金属间电介质层之上形成钝化层。形成与金属线连接的接合焊盘。通过钝化层和金属间电介质层形成具有侧壁钝化层的保护护套，并且位于金属线和集成电路的外边缘之间。

2. 发明申请

US20050127495A1 Method of fabrication of a die oxide ring 有权
标题翻译：芯片氧化物环的制造方法
公开(公告)号：US20050127495A1
公开(公告)日：2005-06-16
申请号：US10734423
申请日：2003-12-12
申请人： Fan Zhang , Bei Zhang , Wuping Liu , Kho Chok , Liang Hsia , Tae Lee , Juan Tan , Xian Wang
发明人： Fan Zhang , Bei Zhang , Wuping Liu , Kho Chok , Liang Hsia , Tae Lee , Juan Tan , Xian Wang
IPC分类号： H01L23/00 , H01L23/31 , H01L23/04 , H01L21/4763
CPC分类号： H01L23/562 , H01L23/3178 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.
摘要翻译：根据本发明的目的，以“氧化物环”的形式提供了一种用于实施本发明的新设计和方法。传统的模具设置有保护环或密封环，其围绕并隔离单个半导体管芯的有源表面积。本发明的“氧化物环”围绕保护环或密封环，并以这种方式形成在管芯的锯切路径和单个化的半导体管芯的有源表面区域之间的机械应力释放缓冲器。

3. 发明申请

US20060030128A1 Structure and method of liner air gap formation 有权
标题翻译：衬里气隙形成的结构和方法
公开(公告)号：US20060030128A1
公开(公告)日：2006-02-09
申请号：US10910499
申请日：2004-08-03
申请人： Xiaomei Bu , Alex See , Tae Lee , Fan Zhang , Yeon Lim , Liang Hsia
发明人： Xiaomei Bu , Alex See , Tae Lee , Fan Zhang , Yeon Lim , Liang Hsia
IPC分类号： H01L21/78
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.
摘要翻译：一种半导体器件的结构和方法，衬底气隙靠近互连和电介质层。介电层形成在衬底上的下介电层和下互连之上。我们在电介质层中形成互连开口。开口具有介电层的侧壁。牺牲衬垫形成在互连开口的侧壁上。形成填充开口的上互连。我们移除牺牲衬垫/垫片以形成（空气）衬垫间隙。

4. 发明申请

US20060286797A1 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects 有权
标题翻译：用于CU互连中的应力迁移和电迁移改进的谷物边界阻塞
公开(公告)号：US20060286797A1
公开(公告)日：2006-12-21
申请号：US11153747
申请日：2005-06-15
申请人： Fan Zhang , Kho Liep , Alex See , Cheng-Cheh Tou , Xiaomei Bu , Tae Lee , Liang Hsia
发明人： Fan Zhang , Kho Liep , Alex See , Cheng-Cheh Tou , Xiaomei Bu , Tae Lee , Liang Hsia
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76859 , H01L21/76856 , H01L21/76864
摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
摘要翻译：用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。稍后通过平坦化处理去除阻挡层。在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

5. 发明申请

US20070197023A1 Entire encapsulation of Cu interconnects using self-aligned CuSiN film 有权
标题翻译：使用自对准CuSiN膜的Cu互连的全封装
公开(公告)号：US20070197023A1
公开(公告)日：2007-08-23
申请号：US11358934
申请日：2006-02-22
申请人： Johnny Widodo , Bei Zhang , Tong Chen , Yong Siew , Fan Zhang , San Liew , John Sudijono , Liang Hsia
发明人： Johnny Widodo , Bei Zhang , Tong Chen , Yong Siew , Fan Zhang , San Liew , John Sudijono , Liang Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L24/03 , H01L24/05 , H01L2224/05073 , H01L2224/05546 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/14 , H01L2924/01039 , H01L2924/00
摘要： A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.
摘要翻译：形成用于互连的CuSiN构成的阻挡层和盖的方法。我们在半导体结构上的电介质层中提供互连开口。通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。然后，我们在填充互连开口的CuSiN层上形成互连。我们可以在互连的顶部表面上形成CuSiN覆盖层。

6. 发明申请

US20060040491A1 Slot designs in wide metal lines 有权
标题翻译：狭槽金属线槽设计
公开(公告)号：US20060040491A1
公开(公告)日：2006-02-23
申请号：US10923123
申请日：2004-08-21
申请人： Yeow Lim , Alex See , Tae Lee , David Vigar , Liang Hsia , Kin Pey
发明人： Yeow Lim , Alex See , Tae Lee , David Vigar , Liang Hsia , Kin Pey
IPC分类号： H01L21/4763
CPC分类号： H01L23/528 , H01L21/0276 , H01L21/288 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76879 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.
摘要翻译：用于宽线槽以减少压力的方法和结构。一种示例性实施例的方法和结构是一种互连结构，包括：包括宽线的互连。宽线有第一个插槽。第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。通孔插头可以从上方或下方接触宽线。另一个示例性实施例是双镶嵌互连结构，包括：双镶嵌形互连件，其包括通孔塞，第一槽和宽线。宽线有第一个插槽。第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。

7. 发明申请

US20060234479A1 Implantation-less approach to fabricating strained semiconductor on isolation wafers 有权
标题翻译：无离子方法在隔离晶圆上制造应变半导体
公开(公告)号：US20060234479A1
公开(公告)日：2006-10-19
申请号：US11107712
申请日：2005-04-15
申请人： Jinping Liu , Dong Sohn , Liang Hsia
发明人： Jinping Liu , Dong Sohn , Liang Hsia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/36 , H01L31/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02395 , H01L21/02447 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/76262 , H01L29/78 , Y10S438/933
摘要： A method of fabrication of semiconductor substrate structure comprising the following. A buffer layer is formed on the Si Substrate. We form a SiGe layer on the novel buffer layer. The buffer layer has defects therein so that the buffer layer is oxidized to form a buried isolation layer comprised of silicon oxide and an oxide layer and oxidize the SiGe layer for form a oxide layer. The oxide layer is then removed. An upper semiconductor layer (e.g., Si, SiGe or Ge layer) is epitaxially formed on the SiGe layer. Devices are formed on said an upper semiconductor layer. The buffer layer can be formed by several aspects.
摘要翻译：一种制造半导体衬底结构的方法，包括以下步骤。在Si基板上形成缓冲层。我们在新型缓冲层上形成SiGe层。缓冲层在其中具有缺陷，使得缓冲层被氧化以形成由氧化硅和氧化物层组成的掩埋隔离层，并氧化SiGe层以形成氧化物层。然后除去氧化物层。在SiGe层上外延形成上半导体层（例如Si，SiGe或Ge层）。器件形成在所述上半导体层上。缓冲层可以由几个方面形成。

8. 发明申请

US20060147813A1 Mask and method to pattern chromeless phase lithography contact hole 有权
标题翻译：掩模和方法来绘制无铬相光刻接触孔
公开(公告)号：US20060147813A1
公开(公告)日：2006-07-06
申请号：US11028421
申请日：2005-01-03
申请人： Sya Tan , Soon Tan , Qun Lin , Hury Chong , Liang Hsia
发明人： Sya Tan , Soon Tan , Qun Lin , Hury Chong , Liang Hsia
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/34
摘要： A chromeless phase shift mask and Method for making and using. The A chromeless phase shift mask is used to pattern contact holes. The chromeless phase shift mask preferably comprises: a first phase shift region and a second phase shfit region; the first region is comprised of a unit cell which is comprised of a rectangular center section and at least three rectangular sections (legs) outwards extending from the rectangular center section. The second region is adjacent to said first region. The interference between the first and second phase shift regions creates a contact hole pattern.
摘要翻译：无色相移掩模和制造和使用方法。 A无铬相移掩模用于对接触孔进行图案化。无铬相移掩模优选地包括：第一相移区域和第二相位区域; 第一区域包括由矩形中心部分和从矩形中心部分向外延伸的至少三个矩形部分（腿）的单元电池。第二区域与所述第一区域相邻。第一和第二相移区域之间的干涉产生接触孔图案。

9. 发明申请

US20060105533A1 Method for engineering hybrid orientation/material semiconductor substrate 审中-公开
标题翻译：工程混合取向/材料半导体衬底的方法
公开(公告)号：US20060105533A1
公开(公告)日：2006-05-18
申请号：US10990180
申请日：2004-11-16
申请人： Yung Chong , Liang Hsia , Chew Ang
发明人： Yung Chong , Liang Hsia , Chew Ang
IPC分类号： H01L21/8228
CPC分类号： H01L21/823807
摘要： The embodiments provide a structure and a method of manufacturing a semiconductor structure that has a different material in the area where PMOS devices will be formed than in the area where NMOS devices will be formed which is characterized as follows. An embodiment comprises the following steps. A substrate is provided. The substrate has a NMOS area and a PMOS area. We form a NMOS mask over the NMOS area. We form a first semiconductor layer over the PMOS area. We remove the mask. We form a second semiconductor layer over the NMOS area. Then we form an isolation region in the substrate between at least portions of the NMOS and the PMOS areas. We form PMOS devices in the PMOS area and form NMOS devices in the NMOS area.
摘要翻译：实施例提供一种制造半导体结构的结构和方法，该半导体结构在将要形成PMOS器件的区域中将具有不同于在其上将形成NMOS器件的区域中的材料，其特征如下。实施例包括以下步骤。提供基板。衬底具有NMOS区域和PMOS区域。我们在NMOS区域上形成NMOS掩模。我们在PMOS区域上形成第一半导体层。我们删除面具。我们在NMOS区域上形成第二个半导体层。然后，在NMOS和PMOS区域的至少一部分之间，在衬底中形成隔离区。我们在PMOS区域中形成PMOS器件，并在NMOS区域中形成NMOS器件。

10. 发明申请

US20050164473A1 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US20050164473A1
公开(公告)日：2005-07-28
申请号：US10763305
申请日：2004-01-23
申请人： Jin Liu , Dong Sohn , Liang Hsia
发明人： Jin Liu , Dong Sohn , Liang Hsia
IPC分类号： C30B29/52 , H01L21/20 , H01L29/10 , C30B1/00
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054 , Y10S438/933
摘要： A method of forming a relaxed silicon-germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon-germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon-germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon-germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon-germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon-germanium layer progresses. In situ growth of an overlying silicon-germanium layer featuring uniform or non-graded germanium content, results in a relaxed silicon-germanium layer with a minimum of dislocations propagating from the underlying graded silicon-germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅 - 锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

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